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2024-02-20 102a0743326a03cd1a1202ceda21e175b7d3575c

 kernel/drivers/fpga/dfl-fme-mgr.c
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@@ -30,8 +30,8 @@
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 #define FME_PR_STS		0x10
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 #define FME_PR_DATA		0x18
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 #define FME_PR_ERR		0x20
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-#define FME_PR_INTFC_ID_H	0xA8
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-#define FME_PR_INTFC_ID_L	0xB0
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+#define FME_PR_INTFC_ID_L	0xA8
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+#define FME_PR_INTFC_ID_H	0xB0
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 /* FME PR Control Register Bitfield */
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 #define FME_PR_CTRL_PR_RST	BIT_ULL(0)  /* Reset PR engine */
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@@ -201,7 +201,7 @@
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 		}
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 		if (count < 4) {
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-			dev_err(dev, "Invaild PR bitstream size\n");
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+			dev_err(dev, "Invalid PR bitstream size\n");
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 			return -EINVAL;
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 		}
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@@ -287,7 +287,6 @@
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 	struct fme_mgr_priv *priv;
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 	struct fpga_manager *mgr;
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 	struct resource *res;
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-	int ret;
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 	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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 	if (!priv)
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@@ -309,19 +308,15 @@
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 	fme_mgr_get_compat_id(priv->ioaddr, compat_id);
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-	mgr = fpga_mgr_create(dev, "DFL FME FPGA Manager",
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-			      &fme_mgr_ops, priv);
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+	mgr = devm_fpga_mgr_create(dev, "DFL FME FPGA Manager",
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+				   &fme_mgr_ops, priv);
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 	if (!mgr)
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 		return -ENOMEM;
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 	mgr->compat_id = compat_id;
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 	platform_set_drvdata(pdev, mgr);
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-	ret = fpga_mgr_register(mgr);
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-	if (ret)
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-		fpga_mgr_free(mgr);
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-
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-	return ret;
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+	return fpga_mgr_register(mgr);
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 }
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 static int fme_mgr_remove(struct platform_device *pdev)