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2024-02-20 102a0743326a03cd1a1202ceda21e175b7d3575c 
 kernel/drivers/dma/pl330.c
....@@ -405,6 +405,12 @@
405405 	 */
406406 	BUSY,
407407 	/*
408
+	 * Pause was called while descriptor was BUSY. Due to hardware
409
+	 * limitations, only termination is possible for descriptors
410
+	 * that have been paused.
411
+	 */
412
+	PAUSED,
413
+	/*
408414 	 * Sitting on the channel work_list but xfer done
409415 	 * by PL330 core
410416 	 */
....@@ -541,11 +547,9 @@
541547 	/* For cyclic capability */
542548 	bool cyclic;
543549 	size_t num_periods;
544
-#ifdef CONFIG_NO_GKI
545
-	/* interlace size */
546
-	unsigned int src_interlace_size;
547
-	unsigned int dst_interlace_size;
548
-#endif
550
+
551
+	/* interleaved size */
552
+	struct data_chunk sgl;
549553 };
550554 
551555 struct _xfer_spec {
....@@ -1073,7 +1077,7 @@
10731077 	return true;
10741078 }
10751079 
1076
-static bool _start(struct pl330_thread *thrd)
1080
+static bool pl330_start_thread(struct pl330_thread *thrd)
10771081 {
10781082 	switch (_state(thrd)) {
10791083 	case PL330_STATE_FAULT_COMPLETING:
....@@ -1204,7 +1208,7 @@
12041208 				 const struct _xfer_spec *pxs, int cyc,
12051209 				 enum pl330_cond cond)
12061210 {
1207
-	int off = 0;
1211
+	int off = 0, i = 0, burstn = 1;
12081212 
12091213 	/*
12101214 	 * do FLUSHP at beginning to clear any stale dma requests before the
....@@ -1212,30 +1216,36 @@
12121216 	 */
12131217 	if (!(pl330->quirks & PL330_QUIRK_BROKEN_NO_FLUSHP))
12141218 		off += _emit_FLUSHP(dry_run, &buf[off], pxs->desc->peri);
1219
+
1220
+	if (pxs->desc->sgl.size) {
1221
+		WARN_ON(BYTE_MOD_BURST_LEN(pxs->desc->sgl.size, pxs->ccr));
1222
+		burstn = BYTE_TO_BURST(pxs->desc->sgl.size, pxs->ccr);
1223
+	}
1224
+
12151225 	while (cyc--) {
1216
-		off += _emit_WFP(dry_run, &buf[off], cond, pxs->desc->peri);
1217
-		off += _emit_load(dry_run, &buf[off], cond, pxs->desc->rqtype,
1218
-			pxs->desc->peri);
1219
-		off += _emit_store(dry_run, &buf[off], cond, pxs->desc->rqtype,
1220
-			pxs->desc->peri);
1221
-#ifdef CONFIG_NO_GKI
1226
+		for (i = 0; i < burstn; i++) {
1227
+			off += _emit_WFP(dry_run, &buf[off], cond, pxs->desc->peri);
1228
+			off += _emit_load(dry_run, &buf[off], cond, pxs->desc->rqtype,
1229
+				pxs->desc->peri);
1230
+			off += _emit_store(dry_run, &buf[off], cond, pxs->desc->rqtype,
1231
+				pxs->desc->peri);
1232
+		}
1233
+
12221234 		switch (pxs->desc->rqtype) {
12231235 		case DMA_DEV_TO_MEM:
1224
-
1225
-			if (pxs->desc->dst_interlace_size)
1236
+			if (pxs->desc->sgl.dst_icg)
12261237 				off += _emit_ADDH(dry_run, &buf[off], DST,
1227
-						  pxs->desc->dst_interlace_size);
1238
+						  pxs->desc->sgl.dst_icg);
12281239 			break;
12291240 		case DMA_MEM_TO_DEV:
1230
-			if (pxs->desc->src_interlace_size)
1241
+			if (pxs->desc->sgl.src_icg)
12311242 				off += _emit_ADDH(dry_run, &buf[off], SRC,
1232
-						  pxs->desc->src_interlace_size);
1243
+						  pxs->desc->sgl.src_icg);
12331244 			break;
12341245 		default:
12351246 			WARN_ON(1);
12361247 			break;
12371248 		}
1238
-#endif
12391249 	}
12401250 
12411251 	return off;
....@@ -1450,9 +1460,7 @@
14501460 		off += _emit_LPEND(dry_run, &buf[off], &lpend);
14511461 	}
14521462 
1453
-#ifdef CONFIG_NO_GKI
1454
-	if (!pxs->desc->src_interlace_size &&
1455
-	    !pxs->desc->dst_interlace_size) {
1463
+	if (!pxs->desc->sgl.src_icg && !pxs->desc->sgl.dst_icg) {
14561464 		num_dregs = BYTE_MOD_BURST_LEN(x->bytes, pxs->ccr);
14571465 
14581466 		if (num_dregs) {
....@@ -1460,14 +1468,6 @@
14601468 			off += _emit_MOV(dry_run, &buf[off], CCR, pxs->ccr);
14611469 		}
14621470 	}
1463
-#else
1464
-	num_dregs = BYTE_MOD_BURST_LEN(x->bytes, pxs->ccr);
1465
-
1466
-	if (num_dregs) {
1467
-		off += _dregs(pl330, dry_run, &buf[off], pxs, num_dregs);
1468
-		off += _emit_MOV(dry_run, &buf[off], CCR, pxs->ccr);
1469
-	}
1470
-#endif
14711471 
14721472 	off += _emit_SEV(dry_run, &buf[off], ev);
14731473 
....@@ -1535,26 +1535,18 @@
15351535 		BRST_SIZE(ccr);
15361536 	int off = 0;
15371537 
1538
-#ifdef CONFIG_NO_GKI
1539
-	if (pxs->desc->rqtype == DMA_DEV_TO_MEM)
1540
-		bursts = x->bytes / (BRST_SIZE(ccr) * BRST_LEN(ccr) +
1541
-				     pxs->desc->dst_interlace_size);
1542
-	else if (pxs->desc->rqtype == DMA_MEM_TO_DEV)
1543
-		bursts = x->bytes / (BRST_SIZE(ccr) * BRST_LEN(ccr) +
1544
-				     pxs->desc->src_interlace_size);
1545
-#endif
1538
+	if (pxs->desc->sgl.size)
1539
+		bursts = x->bytes / pxs->desc->sgl.size;
1540
+
15461541 	while (bursts) {
15471542 		c = bursts;
15481543 		off += _loop(pl330, dry_run, &buf[off], &c, pxs);
15491544 		bursts -= c;
15501545 	}
1551
-#ifdef CONFIG_NO_GKI
1552
-	if (!pxs->desc->src_interlace_size &&
1553
-	    !pxs->desc->dst_interlace_size)
1546
+
1547
+	if (!pxs->desc->sgl.src_icg && !pxs->desc->sgl.dst_icg)
15541548 		off += _dregs(pl330, dry_run, &buf[off], pxs, num_dregs);
1555
-#else
1556
-	off += _dregs(pl330, dry_run, &buf[off], pxs, num_dregs);
1557
-#endif
1549
+
15581550 	return off;
15591551 }
15601552 
....@@ -1585,14 +1577,9 @@
15851577 	unsigned long bursts = BYTE_TO_BURST(x->bytes, ccr);
15861578 	int off = 0;
15871579 
1588
-#ifdef CONFIG_NO_GKI
1589
-	if (pxs->desc->rqtype == DMA_DEV_TO_MEM)
1590
-		bursts = x->bytes / (BRST_SIZE(ccr) * BRST_LEN(ccr)
1591
-			+ pxs->desc->dst_interlace_size);
1592
-	else if (pxs->desc->rqtype == DMA_MEM_TO_DEV)
1593
-		bursts = x->bytes / (BRST_SIZE(ccr) * BRST_LEN(ccr)
1594
-			+ pxs->desc->src_interlace_size);
1595
-#endif
1580
+	if (pxs->desc->sgl.size)
1581
+		bursts = x->bytes / pxs->desc->sgl.size;
1582
+
15961583 	/* Setup Loop(s) */
15971584 	off += _loop_cyclic(pl330, dry_run, &buf[off], bursts, pxs, ev);
15981585 
....@@ -1907,7 +1894,7 @@
19071894 					thrd->req[active].desc = NULL;
19081895 					thrd->req_running = -1;
19091896 					/* Get going again ASAP */
1910
-					_start(thrd);
1897
+					pl330_start_thread(thrd);
19111898 				}
19121899 
19131900 				/* For now, just make a list of callbacks to be done */
....@@ -2248,7 +2235,7 @@
22482235 	list_for_each_entry(desc, &pch->work_list, node) {
22492236 
22502237 		/* If already submitted */
2251
-		if (desc->status == BUSY)
2238
+		if (desc->status == BUSY || desc->status == PAUSED)
22522239 			continue;
22532240 
22542241 		ret = pl330_submit_req(pch->thread, desc);
....@@ -2309,7 +2296,7 @@
23092296 	} else {
23102297 		/* Make sure the PL330 Channel thread is active */
23112298 		spin_lock(&pch->thread->dmac->lock);
2312
-		_start(pch->thread);
2299
+		pl330_start_thread(pch->thread);
23132300 		spin_unlock(&pch->thread->dmac->lock);
23142301 	}
23152302 
....@@ -2454,10 +2441,6 @@
24542441 			pch->fifo_addr = slave_config->dst_addr;
24552442 		if (slave_config->dst_addr_width)
24562443 			pch->burst_sz = __ffs(slave_config->dst_addr_width);
2457
-#ifdef CONFIG_NO_GKI
2458
-		if (slave_config->src_interlace_size)
2459
-			pch->slave_config.src_interlace_size = slave_config->src_interlace_size;
2460
-#endif
24612444 		pch->burst_len = fixup_burst_len(slave_config->dst_maxburst,
24622445 			pch->dmac->quirks);
24632446 	} else if (direction == DMA_DEV_TO_MEM) {
....@@ -2465,10 +2448,6 @@
24652448 			pch->fifo_addr = slave_config->src_addr;
24662449 		if (slave_config->src_addr_width)
24672450 			pch->burst_sz = __ffs(slave_config->src_addr_width);
2468
-#ifdef CONFIG_NO_GKI
2469
-		if (slave_config->dst_interlace_size)
2470
-			pch->slave_config.dst_interlace_size = slave_config->dst_interlace_size;
2471
-#endif
24722451 		pch->burst_len = fixup_burst_len(slave_config->src_maxburst,
24732452 			pch->dmac->quirks);
24742453 	}
....@@ -2541,6 +2520,7 @@
25412520 {
25422521 	struct dma_pl330_chan *pch = to_pchan(chan);
25432522 	struct pl330_dmac *pl330 = pch->dmac;
2523
+	struct dma_pl330_desc *desc;
25442524 	unsigned long flags;
25452525 
25462526 	pm_runtime_get_sync(pl330->ddma.dev);
....@@ -2550,6 +2530,10 @@
25502530 	_stop(pch->thread);
25512531 	spin_unlock(&pl330->lock);
25522532 
2533
+	list_for_each_entry(desc, &pch->work_list, node) {
2534
+		if (desc->status == BUSY)
2535
+			desc->status = PAUSED;
2536
+	}
25532537 	spin_unlock_irqrestore(&pch->lock, flags);
25542538 	pm_runtime_mark_last_busy(pl330->ddma.dev);
25552539 	pm_runtime_put_autosuspend(pl330->ddma.dev);
....@@ -2639,7 +2623,7 @@
26392623 		else if (running && desc == running)
26402624 			transferred =
26412625 				pl330_get_current_xferred_count(pch, desc);
2642
-		else if (desc->status == BUSY)
2626
+		else if (desc->status == BUSY || desc->status == PAUSED)
26432627 			/*
26442628 			 * Busy but not running means either just enqueued,
26452629 			 * or finished and not yet marked done
....@@ -2655,6 +2639,9 @@
26552639 			switch (desc->status) {
26562640 			case DONE:
26572641 				ret = DMA_COMPLETE;
2642
+				break;
2643
+			case PAUSED:
2644
+				ret = DMA_PAUSED;
26582645 				break;
26592646 			case PREP:
26602647 			case BUSY:
....@@ -2821,6 +2808,10 @@
28212808 	desc->cyclic = false;
28222809 	desc->num_periods = 1;
28232810 
2811
+	desc->sgl.size = 0;
2812
+	desc->sgl.src_icg = 0;
2813
+	desc->sgl.dst_icg = 0;
2814
+
28242815 	dma_async_tx_descriptor_init(&desc->txd, &pch->chan);
28252816 
28262817 	return desc;
....@@ -2936,10 +2927,82 @@
29362927 	desc->cyclic = true;
29372928 	desc->num_periods = len / period_len;
29382929 	desc->txd.flags = flags;
2930
+
2931
+	return &desc->txd;
2932
+}
2933
+
2934
+static struct dma_async_tx_descriptor *pl330_prep_interleaved_dma(
2935
+	struct dma_chan *chan, struct dma_interleaved_template *xt,
2936
+	unsigned long flags)
2937
+{
2938
+	struct dma_pl330_desc *desc = NULL;
2939
+	struct dma_pl330_chan *pch = to_pchan(chan);
2940
+	dma_addr_t dst = 0, src = 0;
2941
+	size_t size, src_icg, dst_icg, period_bytes, buffer_bytes, full_buffer_bytes;
2942
+	size_t nump = 0, numf = 0;
2943
+
2944
+	if (!xt->numf || !xt->sgl[0].size || xt->frame_size != 1)
2945
+		return NULL;
2946
+
29392947 #ifdef CONFIG_NO_GKI
2940
-	desc->src_interlace_size = pch->slave_config.src_interlace_size;
2941
-	desc->dst_interlace_size = pch->slave_config.dst_interlace_size;
2948
+	nump = xt->nump;
29422949 #endif
2950
+	numf = xt->numf;
2951
+	size = xt->sgl[0].size;
2952
+	period_bytes = size * nump;
2953
+	buffer_bytes = size * numf;
2954
+
2955
+	if (flags & DMA_PREP_REPEAT && (!nump || (numf % nump)))
2956
+		return NULL;
2957
+
2958
+	src_icg = dmaengine_get_src_icg(xt, &xt->sgl[0]);
2959
+	dst_icg = dmaengine_get_dst_icg(xt, &xt->sgl[0]);
2960
+
2961
+	pl330_config_write(chan, &pch->slave_config, xt->dir);
2962
+
2963
+	if (!pl330_prep_slave_fifo(pch, xt->dir))
2964
+		return NULL;
2965
+
2966
+	desc = pl330_get_desc(pch);
2967
+	if (!desc) {
2968
+		dev_err(chan->device->dev, "Failed to get desc\n");
2969
+		return NULL;
2970
+	}
2971
+
2972
+	if (xt->dir == DMA_MEM_TO_DEV) {
2973
+		desc->rqcfg.src_inc = 1;
2974
+		desc->rqcfg.dst_inc = 0;
2975
+		src = xt->src_start;
2976
+		dst = pch->fifo_dma;
2977
+		full_buffer_bytes = (size + src_icg) * numf;
2978
+	} else {
2979
+		desc->rqcfg.src_inc = 0;
2980
+		desc->rqcfg.dst_inc = 1;
2981
+		src = pch->fifo_dma;
2982
+		dst = xt->dst_start;
2983
+		full_buffer_bytes = (size + dst_icg) * numf;
2984
+	}
2985
+
2986
+	desc->rqtype = xt->dir;
2987
+	desc->rqcfg.brst_size = pch->burst_sz;
2988
+	desc->rqcfg.brst_len = pch->burst_len;
2989
+	desc->bytes_requested = full_buffer_bytes;
2990
+	desc->sgl.size = size;
2991
+	desc->sgl.src_icg = src_icg;
2992
+	desc->sgl.dst_icg = dst_icg;
2993
+	desc->txd.flags = flags;
2994
+
2995
+	if (flags & DMA_PREP_REPEAT) {
2996
+		desc->cyclic = true;
2997
+		desc->num_periods = numf / nump;
2998
+		fill_px(&desc->px, dst, src, period_bytes);
2999
+	} else {
3000
+		fill_px(&desc->px, dst, src, buffer_bytes);
3001
+	}
3002
+
3003
+	dev_dbg(chan->device->dev, "size: %zu, src_icg: %zu, dst_icg: %zu, nump: %zu, numf: %zu\n",
3004
+		size, src_icg, dst_icg, nump, numf);
3005
+
29433006 	return &desc->txd;
29443007 }
29453008 
....@@ -3072,10 +3135,6 @@
30723135 		desc->rqcfg.brst_len = pch->burst_len;
30733136 		desc->rqtype = direction;
30743137 		desc->bytes_requested = sg_dma_len(sg);
3075
-#ifdef CONFIG_NO_GKI
3076
-		desc->src_interlace_size = pch->slave_config.src_interlace_size;
3077
-		desc->dst_interlace_size = pch->slave_config.dst_interlace_size;
3078
-#endif
30793138 	}
30803139 
30813140 	/* Return the last desc in the chain */
....@@ -3311,12 +3370,16 @@
33113370 		dma_cap_set(DMA_SLAVE, pd->cap_mask);
33123371 		dma_cap_set(DMA_CYCLIC, pd->cap_mask);
33133372 		dma_cap_set(DMA_PRIVATE, pd->cap_mask);
3373
+		dma_cap_set(DMA_INTERLEAVE, pd->cap_mask);
3374
+		dma_cap_set(DMA_REPEAT, pd->cap_mask);
3375
+		dma_cap_set(DMA_LOAD_EOT, pd->cap_mask);
33143376 	}
33153377 
33163378 	pd->device_alloc_chan_resources = pl330_alloc_chan_resources;
33173379 	pd->device_free_chan_resources = pl330_free_chan_resources;
33183380 	pd->device_prep_dma_memcpy = pl330_prep_dma_memcpy;
33193381 	pd->device_prep_dma_cyclic = pl330_prep_dma_cyclic;
3382
+	pd->device_prep_interleaved_dma = pl330_prep_interleaved_dma;
33203383 	pd->device_tx_status = pl330_tx_status;
33213384 	pd->device_prep_slave_sg = pl330_prep_slave_sg;
33223385 	pd->device_config = pl330_config;