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| 1 | +// SPDX-License-Identifier: GPL-2.0-only |
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1 | 2 | /* |
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2 | 3 | * offload engine driver for the Intel Xscale series of i/o processors |
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3 | 4 | * Copyright © 2006, Intel Corporation. |
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4 | | - * |
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5 | | - * This program is free software; you can redistribute it and/or modify it |
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6 | | - * under the terms and conditions of the GNU General Public License, |
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7 | | - * version 2, as published by the Free Software Foundation. |
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8 | | - * |
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9 | | - * This program is distributed in the hope it will be useful, but WITHOUT |
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10 | | - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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11 | | - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
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12 | | - * more details. |
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13 | | - * |
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14 | 5 | */ |
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15 | 6 | |
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16 | 7 | /* |
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.. | .. |
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25 | 16 | #include <linux/spinlock.h> |
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26 | 17 | #include <linux/interrupt.h> |
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27 | 18 | #include <linux/platform_device.h> |
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| 19 | +#include <linux/prefetch.h> |
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28 | 20 | #include <linux/memory.h> |
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29 | 21 | #include <linux/ioport.h> |
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30 | 22 | #include <linux/raid/pq.h> |
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31 | 23 | #include <linux/slab.h> |
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32 | 24 | |
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33 | | -#include <mach/adma.h> |
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34 | | - |
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| 25 | +#include "iop-adma.h" |
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35 | 26 | #include "dmaengine.h" |
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36 | 27 | |
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37 | 28 | #define to_iop_adma_chan(chan) container_of(chan, struct iop_adma_chan, common) |
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.. | .. |
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125 | 116 | list_for_each_entry_safe(iter, _iter, &iop_chan->chain, |
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126 | 117 | chain_node) { |
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127 | 118 | pr_debug("\tcookie: %d slot: %d busy: %d " |
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128 | | - "this_desc: %#x next_desc: %#llx ack: %d\n", |
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| 119 | + "this_desc: %pad next_desc: %#llx ack: %d\n", |
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129 | 120 | iter->async_tx.cookie, iter->idx, busy, |
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130 | | - iter->async_tx.phys, (u64)iop_desc_get_next_desc(iter), |
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| 121 | + &iter->async_tx.phys, (u64)iop_desc_get_next_desc(iter), |
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131 | 122 | async_tx_test_ack(&iter->async_tx)); |
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132 | 123 | prefetch(_iter); |
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133 | 124 | prefetch(&_iter->async_tx); |
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.. | .. |
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182 | 173 | &iop_chan->chain, chain_node) { |
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183 | 174 | zero_sum_result |= |
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184 | 175 | iop_desc_get_zero_result(grp_iter); |
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185 | | - pr_debug("\titer%d result: %d\n", |
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| 176 | + pr_debug("\titer%d result: %d\n", |
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186 | 177 | grp_iter->idx, zero_sum_result); |
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187 | 178 | slot_cnt -= slots_per_op; |
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188 | 179 | if (slot_cnt == 0) |
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.. | .. |
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247 | 238 | spin_unlock_bh(&iop_chan->lock); |
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248 | 239 | } |
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249 | 240 | |
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250 | | -static void iop_adma_tasklet(unsigned long data) |
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| 241 | +static void iop_adma_tasklet(struct tasklet_struct *t) |
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251 | 242 | { |
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252 | | - struct iop_adma_chan *iop_chan = (struct iop_adma_chan *) data; |
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| 243 | + struct iop_adma_chan *iop_chan = from_tasklet(iop_chan, t, |
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| 244 | + irq_tasklet); |
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253 | 245 | |
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254 | 246 | /* lockdep will flag depedency submissions as potentially |
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255 | 247 | * recursive locking, this is not the case as a dependency |
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.. | .. |
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373 | 365 | struct iop_adma_chan *iop_chan = to_iop_adma_chan(tx->chan); |
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374 | 366 | struct iop_adma_desc_slot *grp_start, *old_chain_tail; |
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375 | 367 | int slot_cnt; |
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376 | | - int slots_per_op; |
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377 | 368 | dma_cookie_t cookie; |
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378 | 369 | dma_addr_t next_dma; |
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379 | 370 | |
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380 | 371 | grp_start = sw_desc->group_head; |
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381 | 372 | slot_cnt = grp_start->slot_cnt; |
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382 | | - slots_per_op = grp_start->slots_per_op; |
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383 | 373 | |
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384 | 374 | spin_lock_bh(&iop_chan->lock); |
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385 | 375 | cookie = dma_cookie_assign(tx); |
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.. | .. |
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417 | 407 | |
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418 | 408 | /** |
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419 | 409 | * iop_adma_alloc_chan_resources - returns the number of allocated descriptors |
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420 | | - * @chan - allocate descriptor resources for this channel |
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421 | | - * @client - current client requesting the channel be ready for requests |
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| 410 | + * @chan: allocate descriptor resources for this channel |
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422 | 411 | * |
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423 | 412 | * Note: We keep the slots for 1 operation on iop_chan->chain at all times. To |
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424 | 413 | * avoid deadlock, via async_xor, num_descs_in_pool must at a minimum be |
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.. | .. |
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428 | 417 | static int iop_adma_alloc_chan_resources(struct dma_chan *chan) |
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429 | 418 | { |
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430 | 419 | char *hw_desc; |
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| 420 | + dma_addr_t dma_desc; |
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431 | 421 | int idx; |
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432 | 422 | struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan); |
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433 | 423 | struct iop_adma_desc_slot *slot = NULL; |
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.. | .. |
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456 | 446 | INIT_LIST_HEAD(&slot->tx_list); |
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457 | 447 | INIT_LIST_HEAD(&slot->chain_node); |
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458 | 448 | INIT_LIST_HEAD(&slot->slot_node); |
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459 | | - hw_desc = (char *) iop_chan->device->dma_desc_pool; |
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460 | | - slot->async_tx.phys = |
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461 | | - (dma_addr_t) &hw_desc[idx * IOP_ADMA_SLOT_SIZE]; |
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| 449 | + dma_desc = iop_chan->device->dma_desc_pool; |
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| 450 | + slot->async_tx.phys = dma_desc + idx * IOP_ADMA_SLOT_SIZE; |
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462 | 451 | slot->idx = idx; |
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463 | 452 | |
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464 | 453 | spin_lock_bh(&iop_chan->lock); |
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.. | .. |
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1308 | 1297 | goto err_free_adev; |
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1309 | 1298 | } |
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1310 | 1299 | |
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1311 | | - dev_dbg(&pdev->dev, "%s: allocated descriptor pool virt %p phys %p\n", |
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1312 | | - __func__, adev->dma_desc_pool_virt, |
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1313 | | - (void *) adev->dma_desc_pool); |
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| 1300 | + dev_dbg(&pdev->dev, "%s: allocated descriptor pool virt %p phys %pad\n", |
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| 1301 | + __func__, adev->dma_desc_pool_virt, &adev->dma_desc_pool); |
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1314 | 1302 | |
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1315 | 1303 | adev->id = plat_data->hw_id; |
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1316 | 1304 | |
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.. | .. |
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1363 | 1351 | ret = -ENOMEM; |
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1364 | 1352 | goto err_free_iop_chan; |
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1365 | 1353 | } |
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1366 | | - tasklet_init(&iop_chan->irq_tasklet, iop_adma_tasklet, (unsigned long) |
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1367 | | - iop_chan); |
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| 1354 | + tasklet_setup(&iop_chan->irq_tasklet, iop_adma_tasklet); |
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1368 | 1355 | |
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1369 | 1356 | /* clear errors before enabling interrupts */ |
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1370 | 1357 | iop_adma_device_clear_err_status(iop_chan); |
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1371 | 1358 | |
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1372 | 1359 | for (i = 0; i < 3; i++) { |
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1373 | | - irq_handler_t handler[] = { iop_adma_eot_handler, |
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1374 | | - iop_adma_eoc_handler, |
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1375 | | - iop_adma_err_handler }; |
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| 1360 | + static const irq_handler_t handler[] = { |
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| 1361 | + iop_adma_eot_handler, |
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| 1362 | + iop_adma_eoc_handler, |
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| 1363 | + iop_adma_err_handler |
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| 1364 | + }; |
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1376 | 1365 | int irq = platform_get_irq(pdev, i); |
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1377 | 1366 | if (irq < 0) { |
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1378 | 1367 | ret = -ENXIO; |
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