hc
2024-02-20 102a0743326a03cd1a1202ceda21e175b7d3575c
kernel/drivers/dma/ep93xx_dma.c
....@@ -1,3 +1,4 @@
1
+// SPDX-License-Identifier: GPL-2.0-or-later
12 /*
23 * Driver for the Cirrus Logic EP93xx DMA Controller
34 *
....@@ -11,11 +12,6 @@
1112 * Copyright (C) 2009 Ryan Mallon <rmallon@gmail.com>
1213 *
1314 * This driver is based on dw_dmac and amba-pl08x drivers.
14
- *
15
- * This program is free software; you can redistribute it and/or modify
16
- * it under the terms of the GNU General Public License as published by
17
- * the Free Software Foundation; either version 2 of the License, or
18
- * (at your option) any later version.
1915 */
2016
2117 #include <linux/clk.h>
....@@ -109,6 +105,9 @@
109105 #define DMA_MAX_CHAN_DESCRIPTORS 32
110106
111107 struct ep93xx_dma_engine;
108
+static int ep93xx_dma_slave_config_write(struct dma_chan *chan,
109
+ enum dma_transfer_direction dir,
110
+ struct dma_slave_config *config);
112111
113112 /**
114113 * struct ep93xx_dma_desc - EP93xx specific transaction descriptor
....@@ -148,6 +147,7 @@
148147 * is set via .device_config before slave operation is
149148 * prepared
150149 * @runtime_ctrl: M2M runtime values for the control register.
150
+ * @slave_config: slave configuration
151151 *
152152 * As EP93xx DMA controller doesn't support real chained DMA descriptors we
153153 * will have slightly different scheme here: @active points to a head of
....@@ -180,6 +180,7 @@
180180 struct list_head free_list;
181181 u32 runtime_addr;
182182 u32 runtime_ctrl;
183
+ struct dma_slave_config slave_config;
183184 };
184185
185186 /**
....@@ -187,6 +188,7 @@
187188 * @dma_dev: holds the dmaengine device
188189 * @m2m: is this an M2M or M2P device
189190 * @hw_setup: method which sets the channel up for operation
191
+ * @hw_synchronize: synchronizes DMA channel termination to current context
190192 * @hw_shutdown: shuts the channel down and flushes whatever is left
191193 * @hw_submit: pushes active descriptor(s) to the hardware
192194 * @hw_interrupt: handle the interrupt
....@@ -743,9 +745,9 @@
743745 spin_unlock_irqrestore(&edmac->lock, flags);
744746 }
745747
746
-static void ep93xx_dma_tasklet(unsigned long data)
748
+static void ep93xx_dma_tasklet(struct tasklet_struct *t)
747749 {
748
- struct ep93xx_dma_chan *edmac = (struct ep93xx_dma_chan *)data;
750
+ struct ep93xx_dma_chan *edmac = from_tasklet(edmac, t, tasklet);
749751 struct ep93xx_dma_desc *desc, *d;
750752 struct dmaengine_desc_callback cb;
751753 LIST_HEAD(list);
....@@ -993,7 +995,7 @@
993995 for (offset = 0; offset < len; offset += bytes) {
994996 desc = ep93xx_dma_desc_get(edmac);
995997 if (!desc) {
996
- dev_warn(chan2dev(edmac), "couln't get descriptor\n");
998
+ dev_warn(chan2dev(edmac), "couldn't get descriptor\n");
997999 goto fail;
9981000 }
9991001
....@@ -1051,6 +1053,8 @@
10511053 return NULL;
10521054 }
10531055
1056
+ ep93xx_dma_slave_config_write(chan, dir, &edmac->slave_config);
1057
+
10541058 first = NULL;
10551059 for_each_sg(sgl, sg, sg_len, i) {
10561060 size_t len = sg_dma_len(sg);
....@@ -1063,7 +1067,7 @@
10631067
10641068 desc = ep93xx_dma_desc_get(edmac);
10651069 if (!desc) {
1066
- dev_warn(chan2dev(edmac), "couln't get descriptor\n");
1070
+ dev_warn(chan2dev(edmac), "couldn't get descriptor\n");
10671071 goto fail;
10681072 }
10691073
....@@ -1136,12 +1140,14 @@
11361140 return NULL;
11371141 }
11381142
1143
+ ep93xx_dma_slave_config_write(chan, dir, &edmac->slave_config);
1144
+
11391145 /* Split the buffer into period size chunks */
11401146 first = NULL;
11411147 for (offset = 0; offset < buf_len; offset += period_len) {
11421148 desc = ep93xx_dma_desc_get(edmac);
11431149 if (!desc) {
1144
- dev_warn(chan2dev(edmac), "couln't get descriptor\n");
1150
+ dev_warn(chan2dev(edmac), "couldn't get descriptor\n");
11451151 goto fail;
11461152 }
11471153
....@@ -1227,6 +1233,17 @@
12271233 struct dma_slave_config *config)
12281234 {
12291235 struct ep93xx_dma_chan *edmac = to_ep93xx_dma_chan(chan);
1236
+
1237
+ memcpy(&edmac->slave_config, config, sizeof(*config));
1238
+
1239
+ return 0;
1240
+}
1241
+
1242
+static int ep93xx_dma_slave_config_write(struct dma_chan *chan,
1243
+ enum dma_transfer_direction dir,
1244
+ struct dma_slave_config *config)
1245
+{
1246
+ struct ep93xx_dma_chan *edmac = to_ep93xx_dma_chan(chan);
12301247 enum dma_slave_buswidth width;
12311248 unsigned long flags;
12321249 u32 addr, ctrl;
....@@ -1234,7 +1251,7 @@
12341251 if (!edmac->edma->m2m)
12351252 return -EINVAL;
12361253
1237
- switch (config->direction) {
1254
+ switch (dir) {
12381255 case DMA_DEV_TO_MEM:
12391256 width = config->src_addr_width;
12401257 addr = config->src_addr;
....@@ -1336,8 +1353,7 @@
13361353 INIT_LIST_HEAD(&edmac->active);
13371354 INIT_LIST_HEAD(&edmac->queue);
13381355 INIT_LIST_HEAD(&edmac->free_list);
1339
- tasklet_init(&edmac->tasklet, ep93xx_dma_tasklet,
1340
- (unsigned long)edmac);
1356
+ tasklet_setup(&edmac->tasklet, ep93xx_dma_tasklet);
13411357
13421358 list_add_tail(&edmac->chan.device_node,
13431359 &dma_dev->channels);