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2024-02-20 102a0743326a03cd1a1202ceda21e175b7d3575c

 kernel/drivers/cpufreq/imx6q-cpufreq.c
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..
@@ -1,15 +1,11 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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 /*
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  * Copyright (C) 2013 Freescale Semiconductor, Inc.
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License version 2 as
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- * published by the Free Software Foundation.
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  */
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 #include <linux/clk.h>
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 #include <linux/cpu.h>
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 #include <linux/cpufreq.h>
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-#include <linux/cpu_cooling.h>
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 #include <linux/err.h>
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 #include <linux/module.h>
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 #include <linux/nvmem-consumer.h>
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@@ -52,8 +48,6 @@
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 };
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 static struct device *cpu_dev;
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-static struct thermal_cooling_device *cdev;
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-static bool free_opp;
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 static struct cpufreq_frequency_table *freq_table;
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 static unsigned int max_freq;
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 static unsigned int transition_latency;
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@@ -177,65 +171,40 @@
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 	/* scaling down?  scale voltage after frequency */
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 	if (new_freq < old_freq) {
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 		ret = regulator_set_voltage_tol(arm_reg, volt, 0);
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-		if (ret) {
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+		if (ret)
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 			dev_warn(cpu_dev,
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 				 "failed to scale vddarm down: %d\n", ret);
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-			ret = 0;
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-		}
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 		ret = regulator_set_voltage_tol(soc_reg, imx6_soc_volt[index], 0);
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-		if (ret) {
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+		if (ret)
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 			dev_warn(cpu_dev, "failed to scale vddsoc down: %d\n", ret);
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-			ret = 0;
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-		}
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 		if (!IS_ERR(pu_reg)) {
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 			ret = regulator_set_voltage_tol(pu_reg, imx6_soc_volt[index], 0);
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-			if (ret) {
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+			if (ret)
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 				dev_warn(cpu_dev, "failed to scale vddpu down: %d\n", ret);
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-				ret = 0;
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-			}
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 		}
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 	}
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 	return 0;
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 }
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-static void imx6q_cpufreq_ready(struct cpufreq_policy *policy)
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-{
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-	cdev = of_cpufreq_cooling_register(policy);
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-
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-	if (!cdev)
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-		dev_err(cpu_dev,
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-			"running cpufreq without cooling device: %ld\n",
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-			PTR_ERR(cdev));
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-}
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-
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 static int imx6q_cpufreq_init(struct cpufreq_policy *policy)
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 {
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-	int ret;
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-
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 	policy->clk = clks[ARM].clk;
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-	ret = cpufreq_generic_init(policy, freq_table, transition_latency);
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+	cpufreq_generic_init(policy, freq_table, transition_latency);
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 	policy->suspend_freq = max_freq;
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-
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-	return ret;
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-}
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-
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-static int imx6q_cpufreq_exit(struct cpufreq_policy *policy)
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-{
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-	cpufreq_cooling_unregister(cdev);
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+	dev_pm_opp_of_register_em(cpu_dev, policy->cpus);
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 	return 0;
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 }
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 static struct cpufreq_driver imx6q_cpufreq_driver = {
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-	.flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK,
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+	.flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK |
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+		 CPUFREQ_IS_COOLING_DEV,
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 	.verify = cpufreq_generic_frequency_table_verify,
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 	.target_index = imx6q_set_target,
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 	.get = cpufreq_generic_get,
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 	.init = imx6q_cpufreq_init,
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-	.exit = imx6q_cpufreq_exit,
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 	.name = "imx6q-cpufreq",
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-	.ready = imx6q_cpufreq_ready,
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 	.attr = cpufreq_generic_attr,
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 	.suspend = cpufreq_generic_suspend,
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 };
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@@ -246,31 +215,41 @@
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 #define OCOTP_CFG3_SPEED_996MHZ		0x2
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 #define OCOTP_CFG3_SPEED_852MHZ		0x1
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-static void imx6q_opp_check_speed_grading(struct device *dev)
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+static int imx6q_opp_check_speed_grading(struct device *dev)
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 {
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 	struct device_node *np;
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 	void __iomem *base;
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 	u32 val;
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+	int ret;
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-	np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-ocotp");
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-	if (!np)
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-		return;
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+	if (of_find_property(dev->of_node, "nvmem-cells", NULL)) {
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+		ret = nvmem_cell_read_u32(dev, "speed_grade", &val);
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+		if (ret)
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+			return ret;
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+	} else {
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+		np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-ocotp");
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+		if (!np)
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+			return -ENOENT;
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-	base = of_iomap(np, 0);
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-	if (!base) {
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-		dev_err(dev, "failed to map ocotp\n");
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-		goto put_node;
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+		base = of_iomap(np, 0);
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+		of_node_put(np);
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+		if (!base) {
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+			dev_err(dev, "failed to map ocotp\n");
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+			return -EFAULT;
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+		}
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+
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+		/*
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+		 * SPEED_GRADING[1:0] defines the max speed of ARM:
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+		 * 2b'11: 1200000000Hz;
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+		 * 2b'10: 996000000Hz;
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+		 * 2b'01: 852000000Hz; -- i.MX6Q Only, exclusive with 996MHz.
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+		 * 2b'00: 792000000Hz;
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+		 * We need to set the max speed of ARM according to fuse map.
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+		 */
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+		val = readl_relaxed(base + OCOTP_CFG3);
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+		iounmap(base);
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 	}
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-	/*
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-	 * SPEED_GRADING[1:0] defines the max speed of ARM:
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-	 * 2b'11: 1200000000Hz;
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-	 * 2b'10: 996000000Hz;
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-	 * 2b'01: 852000000Hz; -- i.MX6Q Only, exclusive with 996MHz.
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-	 * 2b'00: 792000000Hz;
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-	 * We need to set the max speed of ARM according to fuse map.
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-	 */
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-	val = readl_relaxed(base + OCOTP_CFG3);
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 	val >>= OCOTP_CFG3_SPEED_SHIFT;
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 	val &= 0x3;
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..
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@@ -287,9 +266,8 @@
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 			if (dev_pm_opp_disable(dev, 1200000000))
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 				dev_warn(dev, "failed to disable 1.2GHz OPP\n");
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 	}
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-	iounmap(base);
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-put_node:
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-	of_node_put(np);
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+
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+	return 0;
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 }
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 #define OCOTP_CFG3_6UL_SPEED_696MHZ	0x2
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@@ -414,19 +392,16 @@
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 	if (of_machine_is_compatible("fsl,imx6ul") ||
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 	    of_machine_is_compatible("fsl,imx6ull")) {
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 		ret = imx6ul_opp_check_speed_grading(cpu_dev);
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-		if (ret == -EPROBE_DEFER)
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-			return ret;
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-		if (ret) {
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+	} else {
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+		ret = imx6q_opp_check_speed_grading(cpu_dev);
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+	}
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+	if (ret) {
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+		if (ret != -EPROBE_DEFER)
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 			dev_err(cpu_dev, "failed to read ocotp: %d\n",
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 				ret);
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-			return ret;
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-		}
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-	} else {
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-		imx6q_opp_check_speed_grading(cpu_dev);
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+		goto out_free_opp;
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 	}
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404
 
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-	/* Because we have added the OPPs here, we must free them */
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-	free_opp = true;
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 	num = dev_pm_opp_get_opp_count(cpu_dev);
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 	if (num < 0) {
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 		ret = num;
..
..
@@ -528,8 +503,7 @@
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 free_freq_table:
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 	dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table);
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 out_free_opp:
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-	if (free_opp)
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-		dev_pm_opp_of_remove_table(cpu_dev);
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+	dev_pm_opp_of_remove_table(cpu_dev);
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 put_reg:
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 	if (!IS_ERR(arm_reg))
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 		regulator_put(arm_reg);
..
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@@ -549,8 +523,7 @@
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 {
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 	cpufreq_unregister_driver(&imx6q_cpufreq_driver);
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 	dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table);
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-	if (free_opp)
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-		dev_pm_opp_of_remove_table(cpu_dev);
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+	dev_pm_opp_of_remove_table(cpu_dev);
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 	regulator_put(arm_reg);
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 	if (!IS_ERR(pu_reg))
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 		regulator_put(pu_reg);