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hc

2024-02-20 102a0743326a03cd1a1202ceda21e175b7d3575c

 kernel/drivers/clocksource/timer-npcm7xx.c
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@@ -32,7 +32,7 @@
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 #define NPCM7XX_Tx_INTEN		BIT(29)
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 #define NPCM7XX_Tx_COUNTEN		BIT(30)
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 #define NPCM7XX_Tx_ONESHOT		0x0
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-#define NPCM7XX_Tx_OPER			GENMASK(3, 27)
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+#define NPCM7XX_Tx_OPER			GENMASK(28, 27)
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 #define NPCM7XX_Tx_MIN_PRESCALE		0x1
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 #define NPCM7XX_Tx_TDR_MASK_BITS	24
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 #define NPCM7XX_Tx_MAX_CNT		0xFFFFFF
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@@ -84,8 +84,6 @@
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 	val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0);
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 	val &= ~NPCM7XX_Tx_OPER;
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-
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-	val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0);
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 	val |= NPCM7XX_START_ONESHOT_Tx;
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 	writel(val, timer_of_base(to) + NPCM7XX_REG_TCSR0);
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@@ -97,12 +95,11 @@
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 	struct timer_of *to = to_timer_of(evt);
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 	u32 val;
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+	writel(timer_of_period(to), timer_of_base(to) + NPCM7XX_REG_TICR0);
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+
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 	val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0);
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 	val &= ~NPCM7XX_Tx_OPER;
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-
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-	writel(timer_of_period(to), timer_of_base(to) + NPCM7XX_REG_TICR0);
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 	val |= NPCM7XX_START_PERIODIC_Tx;
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-
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 	writel(val, timer_of_base(to) + NPCM7XX_REG_TCSR0);
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 	return 0;