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2024-02-20 102a0743326a03cd1a1202ceda21e175b7d3575c 
 kernel/drivers/clocksource/sh_cmt.c
....@@ -1,16 +1,8 @@
1
+// SPDX-License-Identifier: GPL-2.0
12 /*
23  * SuperH Timer Support - CMT
34  *
45  *  Copyright (C) 2008 Magnus Damm
5
- *
6
- * This program is free software; you can redistribute it and/or modify
7
- * it under the terms of the GNU General Public License as published by
8
- * the Free Software Foundation; either version 2 of the License
9
- *
10
- * This program is distributed in the hope that it will be useful,
11
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
12
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13
- * GNU General Public License for more details.
146  */
157 
168 #include <linux/clk.h>
....@@ -21,6 +13,7 @@
2113 #include <linux/init.h>
2214 #include <linux/interrupt.h>
2315 #include <linux/io.h>
16
+#include <linux/iopoll.h>
2417 #include <linux/ioport.h>
2518 #include <linux/irq.h>
2619 #include <linux/module.h>
....@@ -32,6 +25,10 @@
3225 #include <linux/sh_timer.h>
3326 #include <linux/slab.h>
3427 #include <linux/spinlock.h>
28
+
29
+#ifdef CONFIG_SUPERH
30
+#include <asm/platform_early.h>
31
+#endif
3532 
3633 struct sh_cmt_device;
3734 
....@@ -120,6 +117,7 @@
120117 	void __iomem *mapbase;
121118 	struct clk *clk;
122119 	unsigned long rate;
120
+	unsigned int reg_delay;
123121 
124122 	raw_spinlock_t lock; /* Protect the shared start/stop register */
125123 
....@@ -239,6 +237,8 @@
239237 #define CMCNT 1 /* channel register */
240238 #define CMCOR 2 /* channel register */
241239 
240
+#define CMCLKE	0x1000	/* CLK Enable Register (R-Car Gen2) */
241
+
242242 static inline u32 sh_cmt_read_cmstr(struct sh_cmt_channel *ch)
243243 {
244244 	if (ch->iostart)
....@@ -249,10 +249,17 @@
249249 
250250 static inline void sh_cmt_write_cmstr(struct sh_cmt_channel *ch, u32 value)
251251 {
252
-	if (ch->iostart)
253
-		ch->cmt->info->write_control(ch->iostart, 0, value);
254
-	else
255
-		ch->cmt->info->write_control(ch->cmt->mapbase, 0, value);
252
+	u32 old_value = sh_cmt_read_cmstr(ch);
253
+
254
+	if (value != old_value) {
255
+		if (ch->iostart) {
256
+			ch->cmt->info->write_control(ch->iostart, 0, value);
257
+			udelay(ch->cmt->reg_delay);
258
+		} else {
259
+			ch->cmt->info->write_control(ch->cmt->mapbase, 0, value);
260
+			udelay(ch->cmt->reg_delay);
261
+		}
262
+	}
256263 }
257264 
258265 static inline u32 sh_cmt_read_cmcsr(struct sh_cmt_channel *ch)
....@@ -262,7 +269,12 @@
262269 
263270 static inline void sh_cmt_write_cmcsr(struct sh_cmt_channel *ch, u32 value)
264271 {
265
-	ch->cmt->info->write_control(ch->ioctrl, CMCSR, value);
272
+	u32 old_value = sh_cmt_read_cmcsr(ch);
273
+
274
+	if (value != old_value) {
275
+		ch->cmt->info->write_control(ch->ioctrl, CMCSR, value);
276
+		udelay(ch->cmt->reg_delay);
277
+	}
266278 }
267279 
268280 static inline u32 sh_cmt_read_cmcnt(struct sh_cmt_channel *ch)
....@@ -270,14 +282,33 @@
270282 	return ch->cmt->info->read_count(ch->ioctrl, CMCNT);
271283 }
272284 
273
-static inline void sh_cmt_write_cmcnt(struct sh_cmt_channel *ch, u32 value)
285
+static inline int sh_cmt_write_cmcnt(struct sh_cmt_channel *ch, u32 value)
274286 {
287
+	/* Tests showed that we need to wait 3 clocks here */
288
+	unsigned int cmcnt_delay = DIV_ROUND_UP(3 * ch->cmt->reg_delay, 2);
289
+	u32 reg;
290
+
291
+	if (ch->cmt->info->model > SH_CMT_16BIT) {
292
+		int ret = read_poll_timeout_atomic(sh_cmt_read_cmcsr, reg,
293
+						   !(reg & SH_CMT32_CMCSR_WRFLG),
294
+						   1, cmcnt_delay, false, ch);
295
+		if (ret < 0)
296
+			return ret;
297
+	}
298
+
275299 	ch->cmt->info->write_count(ch->ioctrl, CMCNT, value);
300
+	udelay(cmcnt_delay);
301
+	return 0;
276302 }
277303 
278304 static inline void sh_cmt_write_cmcor(struct sh_cmt_channel *ch, u32 value)
279305 {
280
-	ch->cmt->info->write_count(ch->ioctrl, CMCOR, value);
306
+	u32 old_value = ch->cmt->info->read_count(ch->ioctrl, CMCOR);
307
+
308
+	if (value != old_value) {
309
+		ch->cmt->info->write_count(ch->ioctrl, CMCOR, value);
310
+		udelay(ch->cmt->reg_delay);
311
+	}
281312 }
282313 
283314 static u32 sh_cmt_get_counter(struct sh_cmt_channel *ch, u32 *has_wrapped)
....@@ -321,7 +352,7 @@
321352 
322353 static int sh_cmt_enable(struct sh_cmt_channel *ch)
323354 {
324
-	int k, ret;
355
+	int ret;
325356 
326357 	pm_runtime_get_sync(&ch->cmt->pdev->dev);
327358 	dev_pm_syscore_device(&ch->cmt->pdev->dev, true);
....@@ -349,26 +380,9 @@
349380 	}
350381 
351382 	sh_cmt_write_cmcor(ch, 0xffffffff);
352
-	sh_cmt_write_cmcnt(ch, 0);
383
+	ret = sh_cmt_write_cmcnt(ch, 0);
353384 
354
-	/*
355
-	 * According to the sh73a0 user's manual, as CMCNT can be operated
356
-	 * only by the RCLK (Pseudo 32 KHz), there's one restriction on
357
-	 * modifying CMCNT register; two RCLK cycles are necessary before
358
-	 * this register is either read or any modification of the value
359
-	 * it holds is reflected in the LSI's actual operation.
360
-	 *
361
-	 * While at it, we're supposed to clear out the CMCNT as of this
362
-	 * moment, so make sure it's processed properly here.  This will
363
-	 * take RCLKx2 at maximum.
364
-	 */
365
-	for (k = 0; k < 100; k++) {
366
-		if (!sh_cmt_read_cmcnt(ch))
367
-			break;
368
-		udelay(1);
369
-	}
370
-
371
-	if (sh_cmt_read_cmcnt(ch)) {
385
+	if (ret || sh_cmt_read_cmcnt(ch)) {
372386 		dev_err(&ch->cmt->pdev->dev, "ch%u: cannot clear CMCNT\n",
373387 			ch->index);
374388 		ret = -ETIMEDOUT;
....@@ -668,7 +682,7 @@
668682 		return;
669683 
670684 	sh_cmt_stop(ch, FLAG_CLOCKSOURCE);
671
-	pm_genpd_syscore_poweroff(&ch->cmt->pdev->dev);
685
+	dev_pm_genpd_suspend(&ch->cmt->pdev->dev);
672686 }
673687 
674688 static void sh_cmt_clocksource_resume(struct clocksource *cs)
....@@ -678,7 +692,7 @@
678692 	if (!ch->cs_enabled)
679693 		return;
680694 
681
-	pm_genpd_syscore_poweron(&ch->cmt->pdev->dev);
695
+	dev_pm_genpd_resume(&ch->cmt->pdev->dev);
682696 	sh_cmt_start(ch, FLAG_CLOCKSOURCE);
683697 }
684698 
....@@ -770,7 +784,7 @@
770784 {
771785 	struct sh_cmt_channel *ch = ced_to_sh_cmt(ced);
772786 
773
-	pm_genpd_syscore_poweroff(&ch->cmt->pdev->dev);
787
+	dev_pm_genpd_suspend(&ch->cmt->pdev->dev);
774788 	clk_unprepare(ch->cmt->clk);
775789 }
776790 
....@@ -779,7 +793,7 @@
779793 	struct sh_cmt_channel *ch = ced_to_sh_cmt(ced);
780794 
781795 	clk_prepare(ch->cmt->clk);
782
-	pm_genpd_syscore_poweron(&ch->cmt->pdev->dev);
796
+	dev_pm_genpd_resume(&ch->cmt->pdev->dev);
783797 }
784798 
785799 static int sh_cmt_register_clockevent(struct sh_cmt_channel *ch,
....@@ -790,11 +804,8 @@
790804 	int ret;
791805 
792806 	irq = platform_get_irq(ch->cmt->pdev, ch->index);
793
-	if (irq < 0) {
794
-		dev_err(&ch->cmt->pdev->dev, "ch%u: failed to get irq\n",
795
-			ch->index);
807
+	if (irq < 0)
796808 		return irq;
797
-	}
798809 
799810 	ret = request_irq(irq, sh_cmt_interrupt,
800811 			  IRQF_TIMER | IRQF_IRQPOLL | IRQF_NOBALANCING,
....@@ -856,6 +867,7 @@
856867 				unsigned int hwidx, bool clockevent,
857868 				bool clocksource, struct sh_cmt_device *cmt)
858869 {
870
+	u32 value;
859871 	int ret;
860872 
861873 	/* Skip unused channels. */
....@@ -885,6 +897,11 @@
885897 		ch->iostart = cmt->mapbase + ch->hwidx * 0x100;
886898 		ch->ioctrl = ch->iostart + 0x10;
887899 		ch->timer_bit = 0;
900
+
901
+		/* Enable the clock supply to the channel */
902
+		value = ioread32(cmt->mapbase + CMCLKE);
903
+		value |= BIT(hwidx);
904
+		iowrite32(value, cmt->mapbase + CMCLKE);
888905 		break;
889906 	}
890907 
....@@ -918,7 +935,7 @@
918935 		return -ENXIO;
919936 	}
920937 
921
-	cmt->mapbase = ioremap_nocache(mem->start, resource_size(mem));
938
+	cmt->mapbase = ioremap(mem->start, resource_size(mem));
922939 	if (cmt->mapbase == NULL) {
923940 		dev_err(&cmt->pdev->dev, "failed to remap I/O memory\n");
924941 		return -ENXIO;
....@@ -935,22 +952,48 @@
935952 MODULE_DEVICE_TABLE(platform, sh_cmt_id_table);
936953 
937954 static const struct of_device_id sh_cmt_of_table[] __maybe_unused = {
938
-	{ .compatible = "renesas,cmt-48", .data = &sh_cmt_info[SH_CMT_48BIT] },
955
+	{
956
+		/* deprecated, preserved for backward compatibility */
957
+		.compatible = "renesas,cmt-48",
958
+		.data = &sh_cmt_info[SH_CMT_48BIT]
959
+	},
939960 	{
940961 		/* deprecated, preserved for backward compatibility */
941962 		.compatible = "renesas,cmt-48-gen2",
942963 		.data = &sh_cmt_info[SH_CMT0_RCAR_GEN2]
943964 	},
944
-	{ .compatible = "renesas,rcar-gen2-cmt0", .data = &sh_cmt_info[SH_CMT0_RCAR_GEN2] },
945
-	{ .compatible = "renesas,rcar-gen2-cmt1", .data = &sh_cmt_info[SH_CMT1_RCAR_GEN2] },
965
+	{
966
+		.compatible = "renesas,r8a7740-cmt1",
967
+		.data = &sh_cmt_info[SH_CMT_48BIT]
968
+	},
969
+	{
970
+		.compatible = "renesas,sh73a0-cmt1",
971
+		.data = &sh_cmt_info[SH_CMT_48BIT]
972
+	},
973
+	{
974
+		.compatible = "renesas,rcar-gen2-cmt0",
975
+		.data = &sh_cmt_info[SH_CMT0_RCAR_GEN2]
976
+	},
977
+	{
978
+		.compatible = "renesas,rcar-gen2-cmt1",
979
+		.data = &sh_cmt_info[SH_CMT1_RCAR_GEN2]
980
+	},
981
+	{
982
+		.compatible = "renesas,rcar-gen3-cmt0",
983
+		.data = &sh_cmt_info[SH_CMT0_RCAR_GEN2]
984
+	},
985
+	{
986
+		.compatible = "renesas,rcar-gen3-cmt1",
987
+		.data = &sh_cmt_info[SH_CMT1_RCAR_GEN2]
988
+	},
946989 	{ }
947990 };
948991 MODULE_DEVICE_TABLE(of, sh_cmt_of_table);
949992 
950993 static int sh_cmt_setup(struct sh_cmt_device *cmt, struct platform_device *pdev)
951994 {
952
-	unsigned int mask;
953
-	unsigned int i;
995
+	unsigned int mask, i;
996
+	unsigned long rate;
954997 	int ret;
955998 
956999 	cmt->pdev = pdev;
....@@ -986,17 +1029,21 @@
9861029 	if (ret < 0)
9871030 		goto err_clk_unprepare;
9881031 
989
-	if (cmt->info->width == 16)
990
-		cmt->rate = clk_get_rate(cmt->clk) / 512;
991
-	else
992
-		cmt->rate = clk_get_rate(cmt->clk) / 8;
1032
+	rate = clk_get_rate(cmt->clk);
1033
+	if (!rate) {
1034
+		ret = -EINVAL;
1035
+		goto err_clk_disable;
1036
+	}
9931037 
994
-	clk_disable(cmt->clk);
1038
+	/* We shall wait 2 input clks after register writes */
1039
+	if (cmt->info->model >= SH_CMT_48BIT)
1040
+		cmt->reg_delay = DIV_ROUND_UP(2UL * USEC_PER_SEC, rate);
1041
+	cmt->rate = rate / (cmt->info->width == 16 ? 512 : 8);
9951042 
9961043 	/* Map the memory resource(s). */
9971044 	ret = sh_cmt_map_memory(cmt);
9981045 	if (ret < 0)
999
-		goto err_clk_unprepare;
1046
+		goto err_clk_disable;
10001047 
10011048 	/* Allocate and setup the channels. */
10021049 	cmt->num_channels = hweight8(cmt->hw_channels);
....@@ -1024,6 +1071,8 @@
10241071 		mask &= ~(1 << hwidx);
10251072 	}
10261073 
1074
+	clk_disable(cmt->clk);
1075
+
10271076 	platform_set_drvdata(pdev, cmt);
10281077 
10291078 	return 0;
....@@ -1031,6 +1080,8 @@
10311080 err_unmap:
10321081 	kfree(cmt->channels);
10331082 	iounmap(cmt->mapbase);
1083
+err_clk_disable:
1084
+	clk_disable(cmt->clk);
10341085 err_clk_unprepare:
10351086 	clk_unprepare(cmt->clk);
10361087 err_clk_put:
....@@ -1043,7 +1094,7 @@
10431094 	struct sh_cmt_device *cmt = platform_get_drvdata(pdev);
10441095 	int ret;
10451096 
1046
-	if (!is_early_platform_device(pdev)) {
1097
+	if (!is_sh_early_platform_device(pdev)) {
10471098 		pm_runtime_set_active(&pdev->dev);
10481099 		pm_runtime_enable(&pdev->dev);
10491100 	}
....@@ -1063,7 +1114,7 @@
10631114 		pm_runtime_idle(&pdev->dev);
10641115 		return ret;
10651116 	}
1066
-	if (is_early_platform_device(pdev))
1117
+	if (is_sh_early_platform_device(pdev))
10671118 		return 0;
10681119 
10691120  out:
....@@ -1100,7 +1151,10 @@
11001151 	platform_driver_unregister(&sh_cmt_device_driver);
11011152 }
11021153 
1103
-early_platform_init("earlytimer", &sh_cmt_device_driver);
1154
+#ifdef CONFIG_SUPERH
1155
+sh_early_platform_init("earlytimer", &sh_cmt_device_driver);
1156
+#endif
1157
+
11041158 subsys_initcall(sh_cmt_init);
11051159 module_exit(sh_cmt_exit);
11061160