~hc/RK356X_SDK_RELEASE.git

..	..	@@ -174,21 +174,24 @@
174	174	u32 div_reg[3];
175	175	u32 clk_phase[2];
176	176	u32 fixed_div;
177		- struct clk *clk;
	177	+ struct clk_hw *hw_clk;
178	178	struct socfpga_gate_clk *socfpga_clk;
179	179	const char *clk_name = node->name;
180	180	const char *parent_name[SOCFPGA_MAX_PARENTS];
181	181	struct clk_init_data init;
182	182	struct clk_ops *ops;
183	183	int rc;
	184	+ int err;
184	185
185	186	socfpga_clk = kzalloc(sizeof(*socfpga_clk), GFP_KERNEL);
186	187	if (WARN_ON(!socfpga_clk))
187	188	return;
188	189
189	190	ops = kmemdup(&gateclk_ops, sizeof(gateclk_ops), GFP_KERNEL);
190		- if (WARN_ON(!ops))
	191	+ if (WARN_ON(!ops)) {
	192	+ kfree(socfpga_clk);
191	193	return;
	194	+ }
192	195
193	196	rc = of_property_read_u32_array(node, "clk-gate", clk_gate, 2);
194	197	if (rc)
..	..	@@ -238,12 +241,15 @@
238	241	init.parent_names = parent_name;
239	242	socfpga_clk->hw.hw.init = &init;
240	243
241		- clk = clk_register(NULL, &socfpga_clk->hw.hw);
242		- if (WARN_ON(IS_ERR(clk))) {
	244	+ hw_clk = &socfpga_clk->hw.hw;
	245	+
	246	+ err = clk_hw_register(NULL, hw_clk);
	247	+ if (err) {
	248	+ kfree(ops);
243	249	kfree(socfpga_clk);
244	250	return;
245	251	}
246		- rc = of_clk_add_provider(node, of_clk_src_simple_get, clk);
	252	+ rc = of_clk_add_provider(node, of_clk_src_simple_get, hw_clk);
247	253	if (WARN_ON(rc))
248	254	return;
249	255	}