forked from ~ljy/RK356X_SDK_RELEASE

blame | history | patch | commit | commitdiff
hc
2024-02-20 102a0743326a03cd1a1202ceda21e175b7d3575c 
 kernel/drivers/clk/qcom/gcc-msm8994.c
....@@ -1,13 +1,5 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
12 /* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
2
- *
3
- * This program is free software; you can redistribute it and/or modify
4
- * it under the terms of the GNU General Public License version 2 and
5
- * only version 2 as published by the Free Software Foundation.
6
- *
7
- * This program is distributed in the hope that it will be useful,
8
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
9
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
10
- * GNU General Public License for more details.
113  */
124 
135 #include <linux/kernel.h>
....@@ -28,6 +20,7 @@
2820 #include "clk-rcg.h"
2921 #include "clk-branch.h"
3022 #include "reset.h"
23
+#include "gdsc.h"
3124 
3225 enum {
3326 	P_XO,
....@@ -115,6 +108,7 @@
115108 
116109 static struct clk_alpha_pll_postdiv gpll4 = {
117110 	.offset = 0x1dc0,
111
+	.width = 4,
118112 	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
119113 	.clkr.hw.init = &(struct clk_init_data)
120114 	{
....@@ -1780,6 +1774,32 @@
17801774 	},
17811775 };
17821776 
1777
+static struct clk_branch gcc_lpass_q6_axi_clk = {
1778
+	.halt_reg = 0x0280,
1779
+	.clkr = {
1780
+		.enable_reg = 0x0280,
1781
+		.enable_mask = BIT(0),
1782
+		.hw.init = &(struct clk_init_data)
1783
+		{
1784
+			.name = "gcc_lpass_q6_axi_clk",
1785
+			.ops = &clk_branch2_ops,
1786
+		},
1787
+	},
1788
+};
1789
+
1790
+static struct clk_branch gcc_mss_q6_bimc_axi_clk = {
1791
+	.halt_reg = 0x0284,
1792
+	.clkr = {
1793
+		.enable_reg = 0x0284,
1794
+		.enable_mask = BIT(0),
1795
+		.hw.init = &(struct clk_init_data)
1796
+		{
1797
+			.name = "gcc_mss_q6_bimc_axi_clk",
1798
+			.ops = &clk_branch2_ops,
1799
+		},
1800
+	},
1801
+};
1802
+
17831803 static struct clk_branch gcc_pcie_0_aux_clk = {
17841804 	.halt_reg = 0x1ad4,
17851805 	.clkr = {
....@@ -1793,6 +1813,32 @@
17931813 			},
17941814 			.num_parents = 1,
17951815 			.flags = CLK_SET_RATE_PARENT,
1816
+			.ops = &clk_branch2_ops,
1817
+		},
1818
+	},
1819
+};
1820
+
1821
+static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
1822
+	.halt_reg = 0x1ad0,
1823
+	.clkr = {
1824
+		.enable_reg = 0x1ad0,
1825
+		.enable_mask = BIT(0),
1826
+		.hw.init = &(struct clk_init_data)
1827
+		{
1828
+			.name = "gcc_pcie_0_cfg_ahb_clk",
1829
+			.ops = &clk_branch2_ops,
1830
+		},
1831
+	},
1832
+};
1833
+
1834
+static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
1835
+	.halt_reg = 0x1acc,
1836
+	.clkr = {
1837
+		.enable_reg = 0x1acc,
1838
+		.enable_mask = BIT(0),
1839
+		.hw.init = &(struct clk_init_data)
1840
+		{
1841
+			.name = "gcc_pcie_0_mstr_axi_clk",
17961842 			.ops = &clk_branch2_ops,
17971843 		},
17981844 	},
....@@ -1817,6 +1863,20 @@
18171863 	},
18181864 };
18191865 
1866
+static struct clk_branch gcc_pcie_0_slv_axi_clk = {
1867
+	.halt_reg = 0x1ac8,
1868
+	.halt_check = BRANCH_HALT_DELAY,
1869
+	.clkr = {
1870
+		.enable_reg = 0x1ac8,
1871
+		.enable_mask = BIT(0),
1872
+		.hw.init = &(struct clk_init_data)
1873
+		{
1874
+			.name = "gcc_pcie_0_slv_axi_clk",
1875
+			.ops = &clk_branch2_ops,
1876
+		},
1877
+	},
1878
+};
1879
+
18201880 static struct clk_branch gcc_pcie_1_aux_clk = {
18211881 	.halt_reg = 0x1b54,
18221882 	.clkr = {
....@@ -1830,6 +1890,32 @@
18301890 			},
18311891 			.num_parents = 1,
18321892 			.flags = CLK_SET_RATE_PARENT,
1893
+			.ops = &clk_branch2_ops,
1894
+		},
1895
+	},
1896
+};
1897
+
1898
+static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
1899
+	.halt_reg = 0x1b54,
1900
+	.clkr = {
1901
+		.enable_reg = 0x1b54,
1902
+		.enable_mask = BIT(0),
1903
+		.hw.init = &(struct clk_init_data)
1904
+		{
1905
+			.name = "gcc_pcie_1_cfg_ahb_clk",
1906
+			.ops = &clk_branch2_ops,
1907
+		},
1908
+	},
1909
+};
1910
+
1911
+static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
1912
+	.halt_reg = 0x1b50,
1913
+	.clkr = {
1914
+		.enable_reg = 0x1b50,
1915
+		.enable_mask = BIT(0),
1916
+		.hw.init = &(struct clk_init_data)
1917
+		{
1918
+			.name = "gcc_pcie_1_mstr_axi_clk",
18331919 			.ops = &clk_branch2_ops,
18341920 		},
18351921 	},
....@@ -1854,6 +1940,19 @@
18541940 	},
18551941 };
18561942 
1943
+static struct clk_branch gcc_pcie_1_slv_axi_clk = {
1944
+	.halt_reg = 0x1b48,
1945
+	.clkr = {
1946
+		.enable_reg = 0x1b48,
1947
+		.enable_mask = BIT(0),
1948
+		.hw.init = &(struct clk_init_data)
1949
+		{
1950
+			.name = "gcc_pcie_1_slv_axi_clk",
1951
+			.ops = &clk_branch2_ops,
1952
+		},
1953
+	},
1954
+};
1955
+
18571956 static struct clk_branch gcc_pdm2_clk = {
18581957 	.halt_reg = 0x0ccc,
18591958 	.clkr = {
....@@ -1867,6 +1966,19 @@
18671966 			},
18681967 			.num_parents = 1,
18691968 			.flags = CLK_SET_RATE_PARENT,
1969
+			.ops = &clk_branch2_ops,
1970
+		},
1971
+	},
1972
+};
1973
+
1974
+static struct clk_branch gcc_pdm_ahb_clk = {
1975
+	.halt_reg = 0x0cc4,
1976
+	.clkr = {
1977
+		.enable_reg = 0x0cc4,
1978
+		.enable_mask = BIT(0),
1979
+		.hw.init = &(struct clk_init_data)
1980
+		{
1981
+			.name = "gcc_pdm_ahb_clk",
18701982 			.ops = &clk_branch2_ops,
18711983 		},
18721984 	},
....@@ -1907,6 +2019,23 @@
19072019 	},
19082020 };
19092021 
2022
+static struct clk_branch gcc_sdcc2_ahb_clk = {
2023
+	.halt_reg = 0x0508,
2024
+	.clkr = {
2025
+		.enable_reg = 0x0508,
2026
+		.enable_mask = BIT(0),
2027
+		.hw.init = &(struct clk_init_data)
2028
+		{
2029
+			.name = "gcc_sdcc2_ahb_clk",
2030
+			.parent_names = (const char *[]){
2031
+				"periph_noc_clk_src",
2032
+			},
2033
+			.num_parents = 1,
2034
+			.ops = &clk_branch2_ops,
2035
+		},
2036
+	},
2037
+};
2038
+
19102039 static struct clk_branch gcc_sdcc2_apps_clk = {
19112040 	.halt_reg = 0x0504,
19122041 	.clkr = {
....@@ -1925,6 +2054,23 @@
19252054 	},
19262055 };
19272056 
2057
+static struct clk_branch gcc_sdcc3_ahb_clk = {
2058
+	.halt_reg = 0x0548,
2059
+	.clkr = {
2060
+		.enable_reg = 0x0548,
2061
+		.enable_mask = BIT(0),
2062
+		.hw.init = &(struct clk_init_data)
2063
+		{
2064
+			.name = "gcc_sdcc3_ahb_clk",
2065
+			.parent_names = (const char *[]){
2066
+				"periph_noc_clk_src",
2067
+			},
2068
+			.num_parents = 1,
2069
+			.ops = &clk_branch2_ops,
2070
+		},
2071
+	},
2072
+};
2073
+
19282074 static struct clk_branch gcc_sdcc3_apps_clk = {
19292075 	.halt_reg = 0x0544,
19302076 	.clkr = {
....@@ -1938,6 +2084,23 @@
19382084 			},
19392085 			.num_parents = 1,
19402086 			.flags = CLK_SET_RATE_PARENT,
2087
+			.ops = &clk_branch2_ops,
2088
+		},
2089
+	},
2090
+};
2091
+
2092
+static struct clk_branch gcc_sdcc4_ahb_clk = {
2093
+	.halt_reg = 0x0588,
2094
+	.clkr = {
2095
+		.enable_reg = 0x0588,
2096
+		.enable_mask = BIT(0),
2097
+		.hw.init = &(struct clk_init_data)
2098
+		{
2099
+			.name = "gcc_sdcc4_ahb_clk",
2100
+			.parent_names = (const char *[]){
2101
+				"periph_noc_clk_src",
2102
+			},
2103
+			.num_parents = 1,
19412104 			.ops = &clk_branch2_ops,
19422105 		},
19432106 	},
....@@ -1997,6 +2160,19 @@
19972160 	},
19982161 };
19992162 
2163
+static struct clk_branch gcc_tsif_ahb_clk = {
2164
+	.halt_reg = 0x0d84,
2165
+	.clkr = {
2166
+		.enable_reg = 0x0d84,
2167
+		.enable_mask = BIT(0),
2168
+		.hw.init = &(struct clk_init_data)
2169
+		{
2170
+			.name = "gcc_tsif_ahb_clk",
2171
+			.ops = &clk_branch2_ops,
2172
+		},
2173
+	},
2174
+};
2175
+
20002176 static struct clk_branch gcc_tsif_ref_clk = {
20012177 	.halt_reg = 0x0d88,
20022178 	.clkr = {
....@@ -2010,6 +2186,19 @@
20102186 			},
20112187 			.num_parents = 1,
20122188 			.flags = CLK_SET_RATE_PARENT,
2189
+			.ops = &clk_branch2_ops,
2190
+		},
2191
+	},
2192
+};
2193
+
2194
+static struct clk_branch gcc_ufs_ahb_clk = {
2195
+	.halt_reg = 0x1d4c,
2196
+	.clkr = {
2197
+		.enable_reg = 0x1d4c,
2198
+		.enable_mask = BIT(0),
2199
+		.hw.init = &(struct clk_init_data)
2200
+		{
2201
+			.name = "gcc_ufs_ahb_clk",
20132202 			.ops = &clk_branch2_ops,
20142203 		},
20152204 	},
....@@ -2051,6 +2240,34 @@
20512240 	},
20522241 };
20532242 
2243
+static struct clk_branch gcc_ufs_rx_symbol_0_clk = {
2244
+	.halt_reg = 0x1d60,
2245
+	.halt_check = BRANCH_HALT_DELAY,
2246
+	.clkr = {
2247
+		.enable_reg = 0x1d60,
2248
+		.enable_mask = BIT(0),
2249
+		.hw.init = &(struct clk_init_data)
2250
+		{
2251
+			.name = "gcc_ufs_rx_symbol_0_clk",
2252
+			.ops = &clk_branch2_ops,
2253
+		},
2254
+	},
2255
+};
2256
+
2257
+static struct clk_branch gcc_ufs_rx_symbol_1_clk = {
2258
+	.halt_reg = 0x1d64,
2259
+	.halt_check = BRANCH_HALT_DELAY,
2260
+	.clkr = {
2261
+		.enable_reg = 0x1d64,
2262
+		.enable_mask = BIT(0),
2263
+		.hw.init = &(struct clk_init_data)
2264
+		{
2265
+			.name = "gcc_ufs_rx_symbol_1_clk",
2266
+			.ops = &clk_branch2_ops,
2267
+		},
2268
+	},
2269
+};
2270
+
20542271 static struct clk_branch gcc_ufs_tx_cfg_clk = {
20552272 	.halt_reg = 0x1d50,
20562273 	.clkr = {
....@@ -2064,6 +2281,47 @@
20642281 			},
20652282 			.num_parents = 1,
20662283 			.flags = CLK_SET_RATE_PARENT,
2284
+			.ops = &clk_branch2_ops,
2285
+		},
2286
+	},
2287
+};
2288
+
2289
+static struct clk_branch gcc_ufs_tx_symbol_0_clk = {
2290
+	.halt_reg = 0x1d58,
2291
+	.halt_check = BRANCH_HALT_DELAY,
2292
+	.clkr = {
2293
+		.enable_reg = 0x1d58,
2294
+		.enable_mask = BIT(0),
2295
+		.hw.init = &(struct clk_init_data)
2296
+		{
2297
+			.name = "gcc_ufs_tx_symbol_0_clk",
2298
+			.ops = &clk_branch2_ops,
2299
+		},
2300
+	},
2301
+};
2302
+
2303
+static struct clk_branch gcc_ufs_tx_symbol_1_clk = {
2304
+	.halt_reg = 0x1d5c,
2305
+	.halt_check = BRANCH_HALT_DELAY,
2306
+	.clkr = {
2307
+		.enable_reg = 0x1d5c,
2308
+		.enable_mask = BIT(0),
2309
+		.hw.init = &(struct clk_init_data)
2310
+		{
2311
+			.name = "gcc_ufs_tx_symbol_1_clk",
2312
+			.ops = &clk_branch2_ops,
2313
+		},
2314
+	},
2315
+};
2316
+
2317
+static struct clk_branch gcc_usb2_hs_phy_sleep_clk = {
2318
+	.halt_reg = 0x04ac,
2319
+	.clkr = {
2320
+		.enable_reg = 0x04ac,
2321
+		.enable_mask = BIT(0),
2322
+		.hw.init = &(struct clk_init_data)
2323
+		{
2324
+			.name = "gcc_usb2_hs_phy_sleep_clk",
20672325 			.ops = &clk_branch2_ops,
20682326 		},
20692327 	},
....@@ -2105,6 +2363,19 @@
21052363 	},
21062364 };
21072365 
2366
+static struct clk_branch gcc_usb30_sleep_clk = {
2367
+	.halt_reg = 0x03cc,
2368
+	.clkr = {
2369
+		.enable_reg = 0x03cc,
2370
+		.enable_mask = BIT(0),
2371
+		.hw.init = &(struct clk_init_data)
2372
+		{
2373
+			.name = "gcc_usb30_sleep_clk",
2374
+			.ops = &clk_branch2_ops,
2375
+		},
2376
+	},
2377
+};
2378
+
21082379 static struct clk_branch gcc_usb3_phy_aux_clk = {
21092380 	.halt_reg = 0x1408,
21102381 	.clkr = {
....@@ -2118,6 +2389,19 @@
21182389 			},
21192390 			.num_parents = 1,
21202391 			.flags = CLK_SET_RATE_PARENT,
2392
+			.ops = &clk_branch2_ops,
2393
+		},
2394
+	},
2395
+};
2396
+
2397
+static struct clk_branch gcc_usb_hs_ahb_clk = {
2398
+	.halt_reg = 0x0488,
2399
+	.clkr = {
2400
+		.enable_reg = 0x0488,
2401
+		.enable_mask = BIT(0),
2402
+		.hw.init = &(struct clk_init_data)
2403
+		{
2404
+			.name = "gcc_usb_hs_ahb_clk",
21212405 			.ops = &clk_branch2_ops,
21222406 		},
21232407 	},
....@@ -2139,6 +2423,59 @@
21392423 			.ops = &clk_branch2_ops,
21402424 		},
21412425 	},
2426
+};
2427
+
2428
+static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = {
2429
+	.halt_reg = 0x1a84,
2430
+	.clkr = {
2431
+		.enable_reg = 0x1a84,
2432
+		.enable_mask = BIT(0),
2433
+		.hw.init = &(struct clk_init_data)
2434
+		{
2435
+			.name = "gcc_usb_phy_cfg_ahb2phy_clk",
2436
+			.ops = &clk_branch2_ops,
2437
+		},
2438
+	},
2439
+};
2440
+
2441
+static struct gdsc pcie_gdsc = {
2442
+		.gdscr = 0x1e18,
2443
+		.pd = {
2444
+			.name = "pcie",
2445
+		},
2446
+		.pwrsts = PWRSTS_OFF_ON,
2447
+};
2448
+
2449
+static struct gdsc pcie_0_gdsc = {
2450
+		.gdscr = 0x1ac4,
2451
+		.pd = {
2452
+			.name = "pcie_0",
2453
+		},
2454
+		.pwrsts = PWRSTS_OFF_ON,
2455
+};
2456
+
2457
+static struct gdsc pcie_1_gdsc = {
2458
+		.gdscr = 0x1b44,
2459
+		.pd = {
2460
+			.name = "pcie_1",
2461
+		},
2462
+		.pwrsts = PWRSTS_OFF_ON,
2463
+};
2464
+
2465
+static struct gdsc usb30_gdsc = {
2466
+		.gdscr = 0x3c4,
2467
+		.pd = {
2468
+			.name = "usb30",
2469
+		},
2470
+		.pwrsts = PWRSTS_OFF_ON,
2471
+};
2472
+
2473
+static struct gdsc ufs_gdsc = {
2474
+		.gdscr = 0x1d44,
2475
+		.pd = {
2476
+			.name = "ufs",
2477
+		},
2478
+		.pwrsts = PWRSTS_OFF_ON,
21422479 };
21432480 
21442481 static struct clk_regmap *gcc_msm8994_clocks[] = {
....@@ -2241,26 +2578,64 @@
22412578 	[GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
22422579 	[GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
22432580 	[GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
2581
+	[GCC_LPASS_Q6_AXI_CLK] = &gcc_lpass_q6_axi_clk.clkr,
2582
+	[GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr,
22442583 	[GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
2584
+	[GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
2585
+	[GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
22452586 	[GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
2587
+	[GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
22462588 	[GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,
2589
+	[GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr,
2590
+	[GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr,
22472591 	[GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,
2592
+	[GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr,
22482593 	[GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
2249
-	[GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
2250
-	[GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
2251
-	[GCC_SDCC3_APPS_CLK] = &gcc_sdcc3_apps_clk.clkr,
2252
-	[GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
2594
+	[GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
22532595 	[GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
2596
+	[GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
2597
+	[GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
2598
+	[GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
2599
+	[GCC_SDCC3_AHB_CLK] = &gcc_sdcc3_ahb_clk.clkr,
2600
+	[GCC_SDCC3_APPS_CLK] = &gcc_sdcc3_apps_clk.clkr,
2601
+	[GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
2602
+	[GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
22542603 	[GCC_SYS_NOC_UFS_AXI_CLK] = &gcc_sys_noc_ufs_axi_clk.clkr,
22552604 	[GCC_SYS_NOC_USB3_AXI_CLK] = &gcc_sys_noc_usb3_axi_clk.clkr,
2605
+	[GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr,
22562606 	[GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr,
2607
+	[GCC_UFS_AHB_CLK] = &gcc_ufs_ahb_clk.clkr,
22572608 	[GCC_UFS_AXI_CLK] = &gcc_ufs_axi_clk.clkr,
22582609 	[GCC_UFS_RX_CFG_CLK] = &gcc_ufs_rx_cfg_clk.clkr,
2610
+	[GCC_UFS_RX_SYMBOL_0_CLK] = &gcc_ufs_rx_symbol_0_clk.clkr,
2611
+	[GCC_UFS_RX_SYMBOL_1_CLK] = &gcc_ufs_rx_symbol_1_clk.clkr,
22592612 	[GCC_UFS_TX_CFG_CLK] = &gcc_ufs_tx_cfg_clk.clkr,
2613
+	[GCC_UFS_TX_SYMBOL_0_CLK] = &gcc_ufs_tx_symbol_0_clk.clkr,
2614
+	[GCC_UFS_TX_SYMBOL_1_CLK] = &gcc_ufs_tx_symbol_1_clk.clkr,
2615
+	[GCC_USB2_HS_PHY_SLEEP_CLK] = &gcc_usb2_hs_phy_sleep_clk.clkr,
22602616 	[GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr,
22612617 	[GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr,
2618
+	[GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr,
22622619 	[GCC_USB3_PHY_AUX_CLK] = &gcc_usb3_phy_aux_clk.clkr,
2620
+	[GCC_USB_HS_AHB_CLK] = &gcc_usb_hs_ahb_clk.clkr,
22632621 	[GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr,
2622
+	[GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr,
2623
+};
2624
+
2625
+static struct gdsc *gcc_msm8994_gdscs[] = {
2626
+	[PCIE_GDSC] = &pcie_gdsc,
2627
+	[PCIE_0_GDSC] = &pcie_0_gdsc,
2628
+	[PCIE_1_GDSC] = &pcie_1_gdsc,
2629
+	[USB30_GDSC] = &usb30_gdsc,
2630
+	[UFS_GDSC] = &ufs_gdsc,
2631
+};
2632
+
2633
+static const struct qcom_reset_map gcc_msm8994_resets[] = {
2634
+	[USB3_PHY_RESET] = { 0x1400 },
2635
+	[USB3PHY_PHY_RESET] = { 0x1404 },
2636
+	[PCIE_PHY_0_RESET] = { 0x1b18 },
2637
+	[PCIE_PHY_1_RESET] = { 0x1b98 },
2638
+	[QUSB2_PHY_RESET] = { 0x04b8 },
22642639 };
22652640 
22662641 static const struct regmap_config gcc_msm8994_regmap_config = {
....@@ -2275,6 +2650,10 @@
22752650 	.config = &gcc_msm8994_regmap_config,
22762651 	.clks = gcc_msm8994_clocks,
22772652 	.num_clks = ARRAY_SIZE(gcc_msm8994_clocks),
2653
+	.resets = gcc_msm8994_resets,
2654
+	.num_resets = ARRAY_SIZE(gcc_msm8994_resets),
2655
+	.gdscs = gcc_msm8994_gdscs,
2656
+	.num_gdscs = ARRAY_SIZE(gcc_msm8994_gdscs),
22782657 };
22792658 
22802659 static const struct of_device_id gcc_msm8994_match_table[] = {