~hc/RK356X_SDK_RELEASE.git

..	..	@@ -1,14 +1,6 @@
	1	+// SPDX-License-Identifier: GPL-2.0-only
1	2	/*
2	3	* Copyright (c) 2017, The Linux Foundation. All rights reserved.
3		- *
4		- * This software is licensed under the terms of the GNU General Public
5		- * License version 2, as published by the Free Software Foundation, and
6		- * may be copied, distributed, and modified under those terms.
7		- *
8		- * This program is distributed in the hope that it will be useful,
9		- * but WITHOUT ANY WARRANTY; without even the implied warranty of
10		- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11		- * GNU General Public License for more details.
12	4	*/
13	5
14	6	#include <linux/kernel.h>
..	..	@@ -66,11 +58,6 @@
66	58	{ P_XO, 0 },
67	59	{ P_GPLL0, 1 },
68	60	{ P_GPLL0_DIV2, 4 },
69		-};
70		-
71		-static const char * const gcc_xo_gpll0[] = {
72		- "xo",
73		- "gpll0",
74	61	};
75	62
76	63	static const struct parent_map gcc_xo_gpll0_map[] = {
..	..	@@ -675,6 +662,7 @@
675	662	},
676	663	.num_parents = 1,
677	664	.ops = &clk_branch2_ops,
	665	+ .flags = CLK_IS_CRITICAL,
678	666	},
679	667	},
680	668	};
..	..	@@ -964,6 +952,11 @@
964	952	},
965	953	};
966	954
	955	+static const struct clk_parent_data gcc_xo_gpll0[] = {
	956	+ { .fw_name = "xo" },
	957	+ { .hw = &gpll0.clkr.hw },
	958	+};
	959	+
967	960	static const struct freq_tbl ftbl_pcie_axi_clk_src[] = {
968	961	F(19200000, P_XO, 1, 0, 0),
969	962	F(200000000, P_GPLL0, 4, 0, 0),
..	..	@@ -977,7 +970,7 @@
977	970	.parent_map = gcc_xo_gpll0_map,
978	971	.clkr.hw.init = &(struct clk_init_data){
979	972	.name = "pcie0_axi_clk_src",
980		- .parent_names = gcc_xo_gpll0,
	973	+ .parent_data = gcc_xo_gpll0,
981	974	.num_parents = 2,
982	975	.ops = &clk_rcg2_ops,
983	976	},
..	..	@@ -1024,7 +1017,7 @@
1024	1017	.parent_map = gcc_xo_gpll0_map,
1025	1018	.clkr.hw.init = &(struct clk_init_data){
1026	1019	.name = "pcie1_axi_clk_src",
1027		- .parent_names = gcc_xo_gpll0,
	1020	+ .parent_data = gcc_xo_gpll0,
1028	1021	.num_parents = 2,
1029	1022	.ops = &clk_rcg2_ops,
1030	1023	},
..	..	@@ -1082,7 +1075,7 @@
1082	1075	.name = "sdcc1_apps_clk_src",
1083	1076	.parent_names = gcc_xo_gpll0_gpll2_gpll0_out_main_div2,
1084	1077	.num_parents = 4,
1085		- .ops = &clk_rcg2_ops,
	1078	+ .ops = &clk_rcg2_floor_ops,
1086	1079	},
1087	1080	};
1088	1081
..	..	@@ -1116,7 +1109,7 @@
1116	1109	.name = "sdcc2_apps_clk_src",
1117	1110	.parent_names = gcc_xo_gpll0_gpll2_gpll0_out_main_div2,
1118	1111	.num_parents = 4,
1119		- .ops = &clk_rcg2_ops,
	1112	+ .ops = &clk_rcg2_floor_ops,
1120	1113	},
1121	1114	};
1122	1115
..	..	@@ -1338,7 +1331,7 @@
1338	1331	.parent_map = gcc_xo_gpll0_map,
1339	1332	.clkr.hw.init = &(struct clk_init_data){
1340	1333	.name = "nss_ce_clk_src",
1341		- .parent_names = gcc_xo_gpll0,
	1334	+ .parent_data = gcc_xo_gpll0,
1342	1335	.num_parents = 2,
1343	1336	.ops = &clk_rcg2_ops,
1344	1337	},
..	..	@@ -1796,8 +1789,10 @@
1796	1789	static const struct freq_tbl ftbl_nss_port5_rx_clk_src[] = {
1797	1790	F(19200000, P_XO, 1, 0, 0),
1798	1791	F(25000000, P_UNIPHY1_RX, 12.5, 0, 0),
	1792	+ F(25000000, P_UNIPHY0_RX, 5, 0, 0),
1799	1793	F(78125000, P_UNIPHY1_RX, 4, 0, 0),
1800	1794	F(125000000, P_UNIPHY1_RX, 2.5, 0, 0),
	1795	+ F(125000000, P_UNIPHY0_RX, 1, 0, 0),
1801	1796	F(156250000, P_UNIPHY1_RX, 2, 0, 0),
1802	1797	F(312500000, P_UNIPHY1_RX, 1, 0, 0),
1803	1798	{ }
..	..	@@ -1836,8 +1831,10 @@
1836	1831	static const struct freq_tbl ftbl_nss_port5_tx_clk_src[] = {
1837	1832	F(19200000, P_XO, 1, 0, 0),
1838	1833	F(25000000, P_UNIPHY1_TX, 12.5, 0, 0),
	1834	+ F(25000000, P_UNIPHY0_TX, 5, 0, 0),
1839	1835	F(78125000, P_UNIPHY1_TX, 4, 0, 0),
1840	1836	F(125000000, P_UNIPHY1_TX, 2.5, 0, 0),
	1837	+ F(125000000, P_UNIPHY0_TX, 1, 0, 0),
1841	1838	F(156250000, P_UNIPHY1_TX, 2, 0, 0),
1842	1839	F(312500000, P_UNIPHY1_TX, 1, 0, 0),
1843	1840	{ }
..	..	@@ -1875,8 +1872,10 @@
1875	1872
1876	1873	static const struct freq_tbl ftbl_nss_port6_rx_clk_src[] = {
1877	1874	F(19200000, P_XO, 1, 0, 0),
	1875	+ F(25000000, P_UNIPHY2_RX, 5, 0, 0),
1878	1876	F(25000000, P_UNIPHY2_RX, 12.5, 0, 0),
1879	1877	F(78125000, P_UNIPHY2_RX, 4, 0, 0),
	1878	+ F(125000000, P_UNIPHY2_RX, 1, 0, 0),
1880	1879	F(125000000, P_UNIPHY2_RX, 2.5, 0, 0),
1881	1880	F(156250000, P_UNIPHY2_RX, 2, 0, 0),
1882	1881	F(312500000, P_UNIPHY2_RX, 1, 0, 0),
..	..	@@ -1915,8 +1914,10 @@
1915	1914
1916	1915	static const struct freq_tbl ftbl_nss_port6_tx_clk_src[] = {
1917	1916	F(19200000, P_XO, 1, 0, 0),
	1917	+ F(25000000, P_UNIPHY2_TX, 5, 0, 0),
1918	1918	F(25000000, P_UNIPHY2_TX, 12.5, 0, 0),
1919	1919	F(78125000, P_UNIPHY2_TX, 4, 0, 0),
	1920	+ F(125000000, P_UNIPHY2_TX, 1, 0, 0),
1920	1921	F(125000000, P_UNIPHY2_TX, 2.5, 0, 0),
1921	1922	F(156250000, P_UNIPHY2_TX, 2, 0, 0),
1922	1923	F(312500000, P_UNIPHY2_TX, 1, 0, 0),
..	..	@@ -3354,6 +3355,7 @@
3354	3355
3355	3356	static struct clk_branch gcc_ubi0_ahb_clk = {
3356	3357	.halt_reg = 0x6820c,
	3358	+ .halt_check = BRANCH_HALT_DELAY,
3357	3359	.clkr = {
3358	3360	.enable_reg = 0x6820c,
3359	3361	.enable_mask = BIT(0),
..	..	@@ -3371,6 +3373,7 @@
3371	3373
3372	3374	static struct clk_branch gcc_ubi0_axi_clk = {
3373	3375	.halt_reg = 0x68200,
	3376	+ .halt_check = BRANCH_HALT_DELAY,
3374	3377	.clkr = {
3375	3378	.enable_reg = 0x68200,
3376	3379	.enable_mask = BIT(0),
..	..	@@ -3388,6 +3391,7 @@
3388	3391
3389	3392	static struct clk_branch gcc_ubi0_nc_axi_clk = {
3390	3393	.halt_reg = 0x68204,
	3394	+ .halt_check = BRANCH_HALT_DELAY,
3391	3395	.clkr = {
3392	3396	.enable_reg = 0x68204,
3393	3397	.enable_mask = BIT(0),
..	..	@@ -3405,6 +3409,7 @@
3405	3409
3406	3410	static struct clk_branch gcc_ubi0_core_clk = {
3407	3411	.halt_reg = 0x68210,
	3412	+ .halt_check = BRANCH_HALT_DELAY,
3408	3413	.clkr = {
3409	3414	.enable_reg = 0x68210,
3410	3415	.enable_mask = BIT(0),
..	..	@@ -3422,6 +3427,7 @@
3422	3427
3423	3428	static struct clk_branch gcc_ubi0_mpt_clk = {
3424	3429	.halt_reg = 0x68208,
	3430	+ .halt_check = BRANCH_HALT_DELAY,
3425	3431	.clkr = {
3426	3432	.enable_reg = 0x68208,
3427	3433	.enable_mask = BIT(0),
..	..	@@ -3439,6 +3445,7 @@
3439	3445
3440	3446	static struct clk_branch gcc_ubi1_ahb_clk = {
3441	3447	.halt_reg = 0x6822c,
	3448	+ .halt_check = BRANCH_HALT_DELAY,
3442	3449	.clkr = {
3443	3450	.enable_reg = 0x6822c,
3444	3451	.enable_mask = BIT(0),
..	..	@@ -3456,6 +3463,7 @@
3456	3463
3457	3464	static struct clk_branch gcc_ubi1_axi_clk = {
3458	3465	.halt_reg = 0x68220,
	3466	+ .halt_check = BRANCH_HALT_DELAY,
3459	3467	.clkr = {
3460	3468	.enable_reg = 0x68220,
3461	3469	.enable_mask = BIT(0),
..	..	@@ -3473,6 +3481,7 @@
3473	3481
3474	3482	static struct clk_branch gcc_ubi1_nc_axi_clk = {
3475	3483	.halt_reg = 0x68224,
	3484	+ .halt_check = BRANCH_HALT_DELAY,
3476	3485	.clkr = {
3477	3486	.enable_reg = 0x68224,
3478	3487	.enable_mask = BIT(0),
..	..	@@ -3490,6 +3499,7 @@
3490	3499
3491	3500	static struct clk_branch gcc_ubi1_core_clk = {
3492	3501	.halt_reg = 0x68230,
	3502	+ .halt_check = BRANCH_HALT_DELAY,
3493	3503	.clkr = {
3494	3504	.enable_reg = 0x68230,
3495	3505	.enable_mask = BIT(0),
..	..	@@ -3507,6 +3517,7 @@
3507	3517
3508	3518	static struct clk_branch gcc_ubi1_mpt_clk = {
3509	3519	.halt_reg = 0x68228,
	3520	+ .halt_check = BRANCH_HALT_DELAY,
3510	3521	.clkr = {
3511	3522	.enable_reg = 0x68228,
3512	3523	.enable_mask = BIT(0),
..	..	@@ -4324,6 +4335,88 @@
4324	4335	},
4325	4336	};
4326	4337
	4338	+static const struct freq_tbl ftbl_pcie_rchng_clk_src[] = {
	4339	+ F(19200000, P_XO, 1, 0, 0),
	4340	+ F(100000000, P_GPLL0, 8, 0, 0),
	4341	+ { }
	4342	+};
	4343	+
	4344	+static struct clk_rcg2 pcie0_rchng_clk_src = {
	4345	+ .cmd_rcgr = 0x75070,
	4346	+ .freq_tbl = ftbl_pcie_rchng_clk_src,
	4347	+ .hid_width = 5,
	4348	+ .parent_map = gcc_xo_gpll0_map,
	4349	+ .clkr.hw.init = &(struct clk_init_data){
	4350	+ .name = "pcie0_rchng_clk_src",
	4351	+ .parent_data = gcc_xo_gpll0,
	4352	+ .num_parents = 2,
	4353	+ .ops = &clk_rcg2_ops,
	4354	+ },
	4355	+};
	4356	+
	4357	+static struct clk_branch gcc_pcie0_rchng_clk = {
	4358	+ .halt_reg = 0x75070,
	4359	+ .halt_bit = 31,
	4360	+ .clkr = {
	4361	+ .enable_reg = 0x75070,
	4362	+ .enable_mask = BIT(1),
	4363	+ .hw.init = &(struct clk_init_data){
	4364	+ .name = "gcc_pcie0_rchng_clk",
	4365	+ .parent_hws = (const struct clk_hw *[]){
	4366	+ &pcie0_rchng_clk_src.clkr.hw,
	4367	+ },
	4368	+ .num_parents = 1,
	4369	+ .flags = CLK_SET_RATE_PARENT,
	4370	+ .ops = &clk_branch2_ops,
	4371	+ },
	4372	+ },
	4373	+};
	4374	+
	4375	+static struct clk_branch gcc_pcie0_axi_s_bridge_clk = {
	4376	+ .halt_reg = 0x75048,
	4377	+ .halt_bit = 31,
	4378	+ .clkr = {
	4379	+ .enable_reg = 0x75048,
	4380	+ .enable_mask = BIT(0),
	4381	+ .hw.init = &(struct clk_init_data){
	4382	+ .name = "gcc_pcie0_axi_s_bridge_clk",
	4383	+ .parent_hws = (const struct clk_hw *[]){
	4384	+ &pcie0_axi_clk_src.clkr.hw,
	4385	+ },
	4386	+ .num_parents = 1,
	4387	+ .flags = CLK_SET_RATE_PARENT,
	4388	+ .ops = &clk_branch2_ops,
	4389	+ },
	4390	+ },
	4391	+};
	4392	+
	4393	+static const struct alpha_pll_config ubi32_pll_config = {
	4394	+ .l = 0x4e,
	4395	+ .config_ctl_val = 0x200d4aa8,
	4396	+ .config_ctl_hi_val = 0x3c2,
	4397	+ .main_output_mask = BIT(0),
	4398	+ .aux_output_mask = BIT(1),
	4399	+ .pre_div_val = 0x0,
	4400	+ .pre_div_mask = BIT(12),
	4401	+ .post_div_val = 0x0,
	4402	+ .post_div_mask = GENMASK(9, 8),
	4403	+};
	4404	+
	4405	+static const struct alpha_pll_config nss_crypto_pll_config = {
	4406	+ .l = 0x3e,
	4407	+ .alpha = 0x0,
	4408	+ .alpha_hi = 0x80,
	4409	+ .config_ctl_val = 0x4001055b,
	4410	+ .main_output_mask = BIT(0),
	4411	+ .pre_div_val = 0x0,
	4412	+ .pre_div_mask = GENMASK(14, 12),
	4413	+ .post_div_val = 0x1 << 8,
	4414	+ .post_div_mask = GENMASK(11, 8),
	4415	+ .vco_mask = GENMASK(21, 20),
	4416	+ .vco_val = 0x0,
	4417	+ .alpha_en_mask = BIT(24),
	4418	+};
	4419	+
4327	4420	static struct clk_hw *gcc_ipq8074_hws[] = {
4328	4421	&gpll0_out_main_div2.hw,
4329	4422	&gpll6_out_main_div2.hw,
..	..	@@ -4559,6 +4652,9 @@
4559	4652	[GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
4560	4653	[GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
4561	4654	[GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
	4655	+ [GCC_PCIE0_RCHNG_CLK_SRC] = &pcie0_rchng_clk_src.clkr,
	4656	+ [GCC_PCIE0_RCHNG_CLK] = &gcc_pcie0_rchng_clk.clkr,
	4657	+ [GCC_PCIE0_AXI_S_BRIDGE_CLK] = &gcc_pcie0_axi_s_bridge_clk.clkr,
4562	4658	};
4563	4659
4564	4660	static const struct qcom_reset_map gcc_ipq8074_resets[] = {
..	..	@@ -4686,6 +4782,7 @@
4686	4782	[GCC_PCIE0_AXI_SLAVE_ARES] = { 0x75040, 4 },
4687	4783	[GCC_PCIE0_AHB_ARES] = { 0x75040, 5 },
4688	4784	[GCC_PCIE0_AXI_MASTER_STICKY_ARES] = { 0x75040, 6 },
	4785	+ [GCC_PCIE0_AXI_SLAVE_STICKY_ARES] = { 0x75040, 7 },
4689	4786	[GCC_PCIE1_PIPE_ARES] = { 0x76040, 0 },
4690	4787	[GCC_PCIE1_SLEEP_ARES] = { 0x76040, 1 },
4691	4788	[GCC_PCIE1_CORE_STICKY_ARES] = { 0x76040, 2 },
..	..	@@ -4715,19 +4812,26 @@
4715	4812	.num_clks = ARRAY_SIZE(gcc_ipq8074_clks),
4716	4813	.resets = gcc_ipq8074_resets,
4717	4814	.num_resets = ARRAY_SIZE(gcc_ipq8074_resets),
	4815	+ .clk_hws = gcc_ipq8074_hws,
	4816	+ .num_clk_hws = ARRAY_SIZE(gcc_ipq8074_hws),
4718	4817	};
4719	4818
4720	4819	static int gcc_ipq8074_probe(struct platform_device *pdev)
4721	4820	{
4722		- int ret, i;
	4821	+ struct regmap *regmap;
4723	4822
4724		- for (i = 0; i < ARRAY_SIZE(gcc_ipq8074_hws); i++) {
4725		- ret = devm_clk_hw_register(&pdev->dev, gcc_ipq8074_hws[i]);
4726		- if (ret)
4727		- return ret;
4728		- }
	4823	+ regmap = qcom_cc_map(pdev, &gcc_ipq8074_desc);
	4824	+ if (IS_ERR(regmap))
	4825	+ return PTR_ERR(regmap);
4729	4826
4730		- return qcom_cc_probe(pdev, &gcc_ipq8074_desc);
	4827	+ /* SW Workaround for UBI32 Huayra PLL */
	4828	+ regmap_update_bits(regmap, 0x2501c, BIT(26), BIT(26));
	4829	+
	4830	+ clk_alpha_pll_configure(&ubi32_pll_main, regmap, &ubi32_pll_config);
	4831	+ clk_alpha_pll_configure(&nss_crypto_pll_main, regmap,
	4832	+ &nss_crypto_pll_config);
	4833	+
	4834	+ return qcom_cc_really_probe(pdev, &gcc_ipq8074_desc, regmap);
4731	4835	}
4732	4836
4733	4837	static struct platform_driver gcc_ipq8074_driver = {