add new system file

hc

2024-02-20 102a0743326a03cd1a1202ceda21e175b7d3575c

 kernel/drivers/clk/qcom/gcc-ipq6018.c
..
..
@@ -1654,7 +1654,7 @@
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 		.name = "sdcc1_apps_clk_src",
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 		.parent_data = gcc_xo_gpll0_gpll2_gpll0_out_main_div2,
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 		.num_parents = 4,
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-		.ops = &clk_rcg2_ops,
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+		.ops = &clk_rcg2_floor_ops,
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 	},
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 };
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..
..
@@ -4517,24 +4517,24 @@
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 	[GCC_PCIE0_AHB_ARES] = { 0x75040, 5 },
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 	[GCC_PCIE0_AXI_MASTER_STICKY_ARES] = { 0x75040, 6 },
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 	[GCC_PCIE0_AXI_SLAVE_STICKY_ARES] = { 0x75040, 7 },
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-	[GCC_PPE_FULL_RESET] = { 0x68014, 0 },
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-	[GCC_UNIPHY0_SOFT_RESET] = { 0x56004, 0 },
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+	[GCC_PPE_FULL_RESET] = { .reg = 0x68014, .bitmask = 0xf0000 },
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+	[GCC_UNIPHY0_SOFT_RESET] = { .reg = 0x56004, .bitmask = 0x3ff2 },
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 	[GCC_UNIPHY0_XPCS_RESET] = { 0x56004, 2 },
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-	[GCC_UNIPHY1_SOFT_RESET] = { 0x56104, 0 },
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+	[GCC_UNIPHY1_SOFT_RESET] = { .reg = 0x56104, .bitmask = 0x32 },
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 	[GCC_UNIPHY1_XPCS_RESET] = { 0x56104, 2 },
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-	[GCC_EDMA_HW_RESET] = { 0x68014, 0 },
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-	[GCC_NSSPORT1_RESET] = { 0x68014, 0 },
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-	[GCC_NSSPORT2_RESET] = { 0x68014, 0 },
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-	[GCC_NSSPORT3_RESET] = { 0x68014, 0 },
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-	[GCC_NSSPORT4_RESET] = { 0x68014, 0 },
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-	[GCC_NSSPORT5_RESET] = { 0x68014, 0 },
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-	[GCC_UNIPHY0_PORT1_ARES] = { 0x56004, 0 },
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-	[GCC_UNIPHY0_PORT2_ARES] = { 0x56004, 0 },
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-	[GCC_UNIPHY0_PORT3_ARES] = { 0x56004, 0 },
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-	[GCC_UNIPHY0_PORT4_ARES] = { 0x56004, 0 },
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-	[GCC_UNIPHY0_PORT5_ARES] = { 0x56004, 0 },
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-	[GCC_UNIPHY0_PORT_4_5_RESET] = { 0x56004, 0 },
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-	[GCC_UNIPHY0_PORT_4_RESET] = { 0x56004, 0 },
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+	[GCC_EDMA_HW_RESET] = { .reg = 0x68014, .bitmask = 0x300000 },
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+	[GCC_NSSPORT1_RESET] = { .reg = 0x68014, .bitmask = 0x1000003 },
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+	[GCC_NSSPORT2_RESET] = { .reg = 0x68014, .bitmask = 0x200000c },
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+	[GCC_NSSPORT3_RESET] = { .reg = 0x68014, .bitmask = 0x4000030 },
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+	[GCC_NSSPORT4_RESET] = { .reg = 0x68014, .bitmask = 0x8000300 },
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+	[GCC_NSSPORT5_RESET] = { .reg = 0x68014, .bitmask = 0x10000c00 },
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+	[GCC_UNIPHY0_PORT1_ARES] = { .reg = 0x56004, .bitmask = 0x30 },
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+	[GCC_UNIPHY0_PORT2_ARES] = { .reg = 0x56004, .bitmask = 0xc0 },
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+	[GCC_UNIPHY0_PORT3_ARES] = { .reg = 0x56004, .bitmask = 0x300 },
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+	[GCC_UNIPHY0_PORT4_ARES] = { .reg = 0x56004, .bitmask = 0xc00 },
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+	[GCC_UNIPHY0_PORT5_ARES] = { .reg = 0x56004, .bitmask = 0x3000 },
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+	[GCC_UNIPHY0_PORT_4_5_RESET] = { .reg = 0x56004, .bitmask = 0x3c02 },
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+	[GCC_UNIPHY0_PORT_4_RESET] = { .reg = 0x56004, .bitmask = 0xc02 },
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 	[GCC_LPASS_BCR] = {0x1F000, 0},
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 	[GCC_UBI32_TBU_BCR] = {0x65000, 0},
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 	[GCC_LPASS_TBU_BCR] = {0x6C000, 0},