forked from ~ljy/RK356X_SDK_RELEASE

blame | history | patch | commit | commitdiff
hc
2024-02-20 102a0743326a03cd1a1202ceda21e175b7d3575c 
 kernel/drivers/clk/clk-stm32mp1.c
....@@ -870,7 +870,7 @@
870870 				       spinlock_t *lock)
871871 {
872872 	struct stm32_pll_obj *element;
873
-	struct clk_init_data init = {};
873
+	struct clk_init_data init;
874874 	struct clk_hw *hw;
875875 	int err;
876876 
....@@ -1001,7 +1001,7 @@
10011001 					 spinlock_t *lock)
10021002 {
10031003 	struct timer_cker *tim_ker;
1004
-	struct clk_init_data init = {};
1004
+	struct clk_init_data init;
10051005 	struct clk_hw *hw;
10061006 	int err;
10071007 
....@@ -1402,6 +1402,7 @@
14021402 	G_CRYP1,
14031403 	G_HASH1,
14041404 	G_BKPSRAM,
1405
+	G_DDRPERFM,
14051406 
14061407 	G_LAST
14071408 };
....@@ -1488,6 +1489,7 @@
14881489 	K_GATE(G_STGENRO,	RCC_APB4ENSETR, 20, 0),
14891490 	K_MGATE(G_USBPHY,	RCC_APB4ENSETR, 16, 0),
14901491 	K_GATE(G_IWDG2,		RCC_APB4ENSETR, 15, 0),
1492
+	K_GATE(G_DDRPERFM,	RCC_APB4ENSETR, 8, 0),
14911493 	K_MGATE(G_DSI,		RCC_APB4ENSETR, 4, 0),
14921494 	K_MGATE(G_LTDC,		RCC_APB4ENSETR, 0, 0),
14931495 
....@@ -1661,7 +1663,9 @@
16611663 
16621664 	/*  External / Internal Oscillators */
16631665 	GATE_MP1(CK_HSE, "ck_hse", "clk-hse", 0, RCC_OCENSETR, 8, 0),
1664
-	GATE_MP1(CK_CSI, "ck_csi", "clk-csi", 0, RCC_OCENSETR, 4, 0),
1666
+	/* ck_csi is used by IO compensation and should be critical */
1667
+	GATE_MP1(CK_CSI, "ck_csi", "clk-csi", CLK_IS_CRITICAL,
1668
+		 RCC_OCENSETR, 4, 0),
16651669 	GATE_MP1(CK_HSI, "ck_hsi", "clk-hsi-div", 0, RCC_OCENSETR, 0, 0),
16661670 	GATE(CK_LSI, "ck_lsi", "clk-lsi", 0, RCC_RDLSICR, 0, 0),
16671671 	GATE(CK_LSE, "ck_lse", "clk-lse", 0, RCC_BDCR, 0, 0),
....@@ -1897,6 +1901,7 @@
18971901 	PCLK(CRC1, "crc1", "ck_axi", 0, G_CRC1),
18981902 	PCLK(USBH, "usbh", "ck_axi", 0, G_USBH),
18991903 	PCLK(ETHSTP, "ethstp", "ck_axi", 0, G_ETHSTP),
1904
+	PCLK(DDRPERFM, "ddrperfm", "pclk4", 0, G_DDRPERFM),
19001905 
19011906 	/* Kernel clocks */
19021907 	KCLK(SDMMC1_K, "sdmmc1_k", sdmmc12_src, 0, G_SDMMC1, M_SDMMC12),
....@@ -1957,11 +1962,10 @@
19571962 		  CLK_SET_RATE_NO_REPARENT,
19581963 		  _NO_GATE,
19591964 		  _MMUX(M_ETHCK),
1960
-		  _DIV(RCC_ETHCKSELR, 4, 4, CLK_DIVIDER_ALLOW_ZERO, NULL)),
1965
+		  _DIV(RCC_ETHCKSELR, 4, 4, 0, NULL)),
19611966 
19621967 	/* RTC clock */
1963
-	DIV(NO_ID, "ck_hse_rtc", "ck_hse", 0, RCC_RTCDIVR, 0, 7,
1964
-	    CLK_DIVIDER_ALLOW_ZERO),
1968
+	DIV(NO_ID, "ck_hse_rtc", "ck_hse", 0, RCC_RTCDIVR, 0, 6, 0),
19651969 
19661970 	COMPOSITE(RTC, "ck_rtc", rtc_src, CLK_OPS_PARENT_ENABLE |
19671971 		   CLK_SET_RATE_PARENT,
....@@ -2017,7 +2021,7 @@
20172021 				 void __iomem *base, spinlock_t *lock,
20182022 				 const struct clock_config *cfg)
20192023 {
2020
-	static struct clk_hw **hws;
2024
+	struct clk_hw **hws;
20212025 	struct clk_hw *hw = ERR_PTR(-ENOENT);
20222026 
20232027 	hws = clk_data->hws;
....@@ -2090,7 +2094,7 @@
20902094 
20912095 	base = of_iomap(np, 0);
20922096 	if (!base) {
2093
-		pr_err("%s: unable to map resource", np->name);
2097
+		pr_err("%pOFn: unable to map resource", np);
20942098 		of_node_put(np);
20952099 		return;
20962100 	}