forked from ~ljy/RK356X_SDK_RELEASE

blame | history | patch | commit | commitdiff
hc
2024-02-20 102a0743326a03cd1a1202ceda21e175b7d3575c 
 kernel/drivers/clk/clk-stm32f4.c
....@@ -1,19 +1,8 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
12 /*
23  * Author: Daniel Thompson <daniel.thompson@linaro.org>
34  *
45  * Inspired by clk-asm9260.c .
5
- *
6
- * This program is free software; you can redistribute it and/or modify it
7
- * under the terms and conditions of the GNU General Public License,
8
- * version 2, as published by the Free Software Foundation.
9
- *
10
- * This program is distributed in the hope it will be useful, but WITHOUT
11
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13
- * more details.
14
- *
15
- * You should have received a copy of the GNU General Public License along with
16
- * this program.  If not, see <http://www.gnu.org/licenses/>.
176  */
187 
198 #include <linux/clk-provider.h>
....@@ -140,7 +129,6 @@
140129 	{ STM32F4_RCC_APB2ENR, 20,	"spi5",		"apb2_div" },
141130 	{ STM32F4_RCC_APB2ENR, 21,	"spi6",		"apb2_div" },
142131 	{ STM32F4_RCC_APB2ENR, 22,	"sai1",		"apb2_div" },
143
-	{ STM32F4_RCC_APB2ENR, 26,	"ltdc",		"apb2_div" },
144132 };
145133 
146134 static const struct stm32f4_gate_data stm32f469_gates[] __initconst = {
....@@ -222,7 +210,6 @@
222210 	{ STM32F4_RCC_APB2ENR, 20,	"spi5",		"apb2_div" },
223211 	{ STM32F4_RCC_APB2ENR, 21,	"spi6",		"apb2_div" },
224212 	{ STM32F4_RCC_APB2ENR, 22,	"sai1",		"apb2_div" },
225
-	{ STM32F4_RCC_APB2ENR, 26,	"ltdc",		"apb2_div" },
226213 };
227214 
228215 static const struct stm32f4_gate_data stm32f746_gates[] __initconst = {
....@@ -297,7 +284,84 @@
297284 	{ STM32F4_RCC_APB2ENR, 21,	"spi6",		"apb2_div" },
298285 	{ STM32F4_RCC_APB2ENR, 22,	"sai1",		"apb2_div" },
299286 	{ STM32F4_RCC_APB2ENR, 23,	"sai2",		"apb2_div" },
300
-	{ STM32F4_RCC_APB2ENR, 26,	"ltdc",		"apb2_div" },
287
+};
288
+
289
+static const struct stm32f4_gate_data stm32f769_gates[] __initconst = {
290
+	{ STM32F4_RCC_AHB1ENR,  0,	"gpioa",	"ahb_div" },
291
+	{ STM32F4_RCC_AHB1ENR,  1,	"gpiob",	"ahb_div" },
292
+	{ STM32F4_RCC_AHB1ENR,  2,	"gpioc",	"ahb_div" },
293
+	{ STM32F4_RCC_AHB1ENR,  3,	"gpiod",	"ahb_div" },
294
+	{ STM32F4_RCC_AHB1ENR,  4,	"gpioe",	"ahb_div" },
295
+	{ STM32F4_RCC_AHB1ENR,  5,	"gpiof",	"ahb_div" },
296
+	{ STM32F4_RCC_AHB1ENR,  6,	"gpiog",	"ahb_div" },
297
+	{ STM32F4_RCC_AHB1ENR,  7,	"gpioh",	"ahb_div" },
298
+	{ STM32F4_RCC_AHB1ENR,  8,	"gpioi",	"ahb_div" },
299
+	{ STM32F4_RCC_AHB1ENR,  9,	"gpioj",	"ahb_div" },
300
+	{ STM32F4_RCC_AHB1ENR, 10,	"gpiok",	"ahb_div" },
301
+	{ STM32F4_RCC_AHB1ENR, 12,	"crc",		"ahb_div" },
302
+	{ STM32F4_RCC_AHB1ENR, 18,	"bkpsra",	"ahb_div" },
303
+	{ STM32F4_RCC_AHB1ENR, 20,	"dtcmram",	"ahb_div" },
304
+	{ STM32F4_RCC_AHB1ENR, 21,	"dma1",		"ahb_div" },
305
+	{ STM32F4_RCC_AHB1ENR, 22,	"dma2",		"ahb_div" },
306
+	{ STM32F4_RCC_AHB1ENR, 23,	"dma2d",	"ahb_div" },
307
+	{ STM32F4_RCC_AHB1ENR, 25,	"ethmac",	"ahb_div" },
308
+	{ STM32F4_RCC_AHB1ENR, 26,	"ethmactx",	"ahb_div" },
309
+	{ STM32F4_RCC_AHB1ENR, 27,	"ethmacrx",	"ahb_div" },
310
+	{ STM32F4_RCC_AHB1ENR, 28,	"ethmacptp",	"ahb_div" },
311
+	{ STM32F4_RCC_AHB1ENR, 29,	"otghs",	"ahb_div" },
312
+	{ STM32F4_RCC_AHB1ENR, 30,	"otghsulpi",	"ahb_div" },
313
+
314
+	{ STM32F4_RCC_AHB2ENR,  0,	"dcmi",		"ahb_div" },
315
+	{ STM32F4_RCC_AHB2ENR,  1,	"jpeg",		"ahb_div" },
316
+	{ STM32F4_RCC_AHB2ENR,  4,	"cryp",		"ahb_div" },
317
+	{ STM32F4_RCC_AHB2ENR,  5,	"hash",		"ahb_div" },
318
+	{ STM32F4_RCC_AHB2ENR,  6,	"rng",		"pll48"   },
319
+	{ STM32F4_RCC_AHB2ENR,  7,	"otgfs",	"pll48"   },
320
+
321
+	{ STM32F4_RCC_AHB3ENR,  0,	"fmc",		"ahb_div",
322
+		CLK_IGNORE_UNUSED },
323
+	{ STM32F4_RCC_AHB3ENR,  1,	"qspi",		"ahb_div",
324
+		CLK_IGNORE_UNUSED },
325
+
326
+	{ STM32F4_RCC_APB1ENR,  0,	"tim2",		"apb1_mul" },
327
+	{ STM32F4_RCC_APB1ENR,  1,	"tim3",		"apb1_mul" },
328
+	{ STM32F4_RCC_APB1ENR,  2,	"tim4",		"apb1_mul" },
329
+	{ STM32F4_RCC_APB1ENR,  3,	"tim5",		"apb1_mul" },
330
+	{ STM32F4_RCC_APB1ENR,  4,	"tim6",		"apb1_mul" },
331
+	{ STM32F4_RCC_APB1ENR,  5,	"tim7",		"apb1_mul" },
332
+	{ STM32F4_RCC_APB1ENR,  6,	"tim12",	"apb1_mul" },
333
+	{ STM32F4_RCC_APB1ENR,  7,	"tim13",	"apb1_mul" },
334
+	{ STM32F4_RCC_APB1ENR,  8,	"tim14",	"apb1_mul" },
335
+	{ STM32F4_RCC_APB1ENR, 10,	"rtcapb",	"apb1_mul" },
336
+	{ STM32F4_RCC_APB1ENR, 11,	"wwdg",		"apb1_div" },
337
+	{ STM32F4_RCC_APB1ENR, 13,	"can3",		"apb1_div" },
338
+	{ STM32F4_RCC_APB1ENR, 14,	"spi2",		"apb1_div" },
339
+	{ STM32F4_RCC_APB1ENR, 15,	"spi3",		"apb1_div" },
340
+	{ STM32F4_RCC_APB1ENR, 16,	"spdifrx",	"apb1_div" },
341
+	{ STM32F4_RCC_APB1ENR, 25,	"can1",		"apb1_div" },
342
+	{ STM32F4_RCC_APB1ENR, 26,	"can2",		"apb1_div" },
343
+	{ STM32F4_RCC_APB1ENR, 27,	"cec",		"apb1_div" },
344
+	{ STM32F4_RCC_APB1ENR, 28,	"pwr",		"apb1_div" },
345
+	{ STM32F4_RCC_APB1ENR, 29,	"dac",		"apb1_div" },
346
+
347
+	{ STM32F4_RCC_APB2ENR,  0,	"tim1",		"apb2_mul" },
348
+	{ STM32F4_RCC_APB2ENR,  1,	"tim8",		"apb2_mul" },
349
+	{ STM32F4_RCC_APB2ENR,  7,	"sdmmc2",	"sdmux2" },
350
+	{ STM32F4_RCC_APB2ENR,  8,	"adc1",		"apb2_div" },
351
+	{ STM32F4_RCC_APB2ENR,  9,	"adc2",		"apb2_div" },
352
+	{ STM32F4_RCC_APB2ENR, 10,	"adc3",		"apb2_div" },
353
+	{ STM32F4_RCC_APB2ENR, 11,	"sdmmc1",	"sdmux1" },
354
+	{ STM32F4_RCC_APB2ENR, 12,	"spi1",		"apb2_div" },
355
+	{ STM32F4_RCC_APB2ENR, 13,	"spi4",		"apb2_div" },
356
+	{ STM32F4_RCC_APB2ENR, 14,	"syscfg",	"apb2_div" },
357
+	{ STM32F4_RCC_APB2ENR, 16,	"tim9",		"apb2_mul" },
358
+	{ STM32F4_RCC_APB2ENR, 17,	"tim10",	"apb2_mul" },
359
+	{ STM32F4_RCC_APB2ENR, 18,	"tim11",	"apb2_mul" },
360
+	{ STM32F4_RCC_APB2ENR, 20,	"spi5",		"apb2_div" },
361
+	{ STM32F4_RCC_APB2ENR, 21,	"spi6",		"apb2_div" },
362
+	{ STM32F4_RCC_APB2ENR, 22,	"sai1",		"apb2_div" },
363
+	{ STM32F4_RCC_APB2ENR, 23,	"sai2",		"apb2_div" },
364
+	{ STM32F4_RCC_APB2ENR, 30,	"mdio",		"apb2_div" },
301365 };
302366 
303367 /*
....@@ -317,6 +381,10 @@
317381 static const u64 stm32f746_gate_map[MAX_GATE_MAP] = { 0x000000f17ef417ffull,
318382 						      0x0000000000000003ull,
319383 						      0x04f77f833e01c9ffull };
384
+
385
+static const u64 stm32f769_gate_map[MAX_GATE_MAP] = { 0x000000f37ef417ffull,
386
+						      0x0000000000000003ull,
387
+						      0x44F77F833E01EDFFull };
320388 
321389 static const u64 *stm32f4_gate_map;
322390 
....@@ -396,7 +464,7 @@
396464 					unsigned long flags, u8 bit_idx)
397465 {
398466 	struct clk_apb_mul *am;
399
-	struct clk_init_data init = {};
467
+	struct clk_init_data init;
400468 	struct clk *clk;
401469 
402470 	am = kzalloc(sizeof(*am), GFP_KERNEL);
....@@ -678,7 +746,7 @@
678746 {
679747 	struct stm32f4_pll_div *pll_div;
680748 	struct clk_hw *hw;
681
-	struct clk_init_data init = {};
749
+	struct clk_init_data init;
682750 	int ret;
683751 
684752 	/* allocate the divider */
....@@ -1048,6 +1116,10 @@
10481116 	"no-clock", "lse", "lsi", "hse-rtc"
10491117 };
10501118 
1119
+static const char *pll_src = "pll-src";
1120
+
1121
+static const char *pllsrc_parent[2] = { "hsi", NULL };
1122
+
10511123 static const char *dsi_parent[2] = { NULL, "pll-r" };
10521124 
10531125 static const char *lcd_parent[1] = { "pllsai-r-div" };
....@@ -1071,6 +1143,9 @@
10711143 static const char *uart_parents2[4] = { "apb1_div", "sys", "hsi", "lse" };
10721144 
10731145 static const char *i2c_parents[4] = { "apb1_div", "sys", "hsi", "no-clock" };
1146
+
1147
+static const char * const dfsdm1_src[] = { "apb2_div", "sys" };
1148
+static const char * const adsfdm1_parent[] = { "sai1_clk", "sai2_clk" };
10741149 
10751150 struct stm32_aux_clk {
10761151 	int idx;
....@@ -1313,6 +1388,177 @@
13131388 	},
13141389 };
13151390 
1391
+static const struct stm32_aux_clk stm32f769_aux_clk[] = {
1392
+	{
1393
+		CLK_LCD, "lcd-tft", lcd_parent, ARRAY_SIZE(lcd_parent),
1394
+		NO_MUX, 0, 0,
1395
+		STM32F4_RCC_APB2ENR, 26,
1396
+		CLK_SET_RATE_PARENT
1397
+	},
1398
+	{
1399
+		CLK_I2S, "i2s", i2s_parents, ARRAY_SIZE(i2s_parents),
1400
+		STM32F4_RCC_CFGR, 23, 1,
1401
+		NO_GATE, 0,
1402
+		CLK_SET_RATE_PARENT
1403
+	},
1404
+	{
1405
+		CLK_SAI1, "sai1_clk", sai_parents, ARRAY_SIZE(sai_parents),
1406
+		STM32F4_RCC_DCKCFGR, 20, 3,
1407
+		STM32F4_RCC_APB2ENR, 22,
1408
+		CLK_SET_RATE_PARENT
1409
+	},
1410
+	{
1411
+		CLK_SAI2, "sai2_clk", sai_parents, ARRAY_SIZE(sai_parents),
1412
+		STM32F4_RCC_DCKCFGR, 22, 3,
1413
+		STM32F4_RCC_APB2ENR, 23,
1414
+		CLK_SET_RATE_PARENT
1415
+	},
1416
+	{
1417
+		NO_IDX, "pll48", pll48_parents, ARRAY_SIZE(pll48_parents),
1418
+		STM32F7_RCC_DCKCFGR2, 27, 1,
1419
+		NO_GATE, 0,
1420
+		0
1421
+	},
1422
+	{
1423
+		NO_IDX, "sdmux1", sdmux_parents, ARRAY_SIZE(sdmux_parents),
1424
+		STM32F7_RCC_DCKCFGR2, 28, 1,
1425
+		NO_GATE, 0,
1426
+		0
1427
+	},
1428
+	{
1429
+		NO_IDX, "sdmux2", sdmux_parents, ARRAY_SIZE(sdmux_parents),
1430
+		STM32F7_RCC_DCKCFGR2, 29, 1,
1431
+		NO_GATE, 0,
1432
+		0
1433
+	},
1434
+	{
1435
+		CLK_HDMI_CEC, "hdmi-cec",
1436
+		hdmi_parents, ARRAY_SIZE(hdmi_parents),
1437
+		STM32F7_RCC_DCKCFGR2, 26, 1,
1438
+		NO_GATE, 0,
1439
+		0
1440
+	},
1441
+	{
1442
+		CLK_SPDIF, "spdif-rx",
1443
+		spdif_parent, ARRAY_SIZE(spdif_parent),
1444
+		STM32F7_RCC_DCKCFGR2, 22, 3,
1445
+		STM32F4_RCC_APB2ENR, 23,
1446
+		CLK_SET_RATE_PARENT
1447
+	},
1448
+	{
1449
+		CLK_USART1, "usart1",
1450
+		uart_parents1, ARRAY_SIZE(uart_parents1),
1451
+		STM32F7_RCC_DCKCFGR2, 0, 3,
1452
+		STM32F4_RCC_APB2ENR, 4,
1453
+		CLK_SET_RATE_PARENT,
1454
+	},
1455
+	{
1456
+		CLK_USART2, "usart2",
1457
+		uart_parents2, ARRAY_SIZE(uart_parents1),
1458
+		STM32F7_RCC_DCKCFGR2, 2, 3,
1459
+		STM32F4_RCC_APB1ENR, 17,
1460
+		CLK_SET_RATE_PARENT,
1461
+	},
1462
+	{
1463
+		CLK_USART3, "usart3",
1464
+		uart_parents2, ARRAY_SIZE(uart_parents1),
1465
+		STM32F7_RCC_DCKCFGR2, 4, 3,
1466
+		STM32F4_RCC_APB1ENR, 18,
1467
+		CLK_SET_RATE_PARENT,
1468
+	},
1469
+	{
1470
+		CLK_UART4, "uart4",
1471
+		uart_parents2, ARRAY_SIZE(uart_parents1),
1472
+		STM32F7_RCC_DCKCFGR2, 6, 3,
1473
+		STM32F4_RCC_APB1ENR, 19,
1474
+		CLK_SET_RATE_PARENT,
1475
+	},
1476
+	{
1477
+		CLK_UART5, "uart5",
1478
+		uart_parents2, ARRAY_SIZE(uart_parents1),
1479
+		STM32F7_RCC_DCKCFGR2, 8, 3,
1480
+		STM32F4_RCC_APB1ENR, 20,
1481
+		CLK_SET_RATE_PARENT,
1482
+	},
1483
+	{
1484
+		CLK_USART6, "usart6",
1485
+		uart_parents1, ARRAY_SIZE(uart_parents1),
1486
+		STM32F7_RCC_DCKCFGR2, 10, 3,
1487
+		STM32F4_RCC_APB2ENR, 5,
1488
+		CLK_SET_RATE_PARENT,
1489
+	},
1490
+	{
1491
+		CLK_UART7, "uart7",
1492
+		uart_parents2, ARRAY_SIZE(uart_parents1),
1493
+		STM32F7_RCC_DCKCFGR2, 12, 3,
1494
+		STM32F4_RCC_APB1ENR, 30,
1495
+		CLK_SET_RATE_PARENT,
1496
+	},
1497
+	{
1498
+		CLK_UART8, "uart8",
1499
+		uart_parents2, ARRAY_SIZE(uart_parents1),
1500
+		STM32F7_RCC_DCKCFGR2, 14, 3,
1501
+		STM32F4_RCC_APB1ENR, 31,
1502
+		CLK_SET_RATE_PARENT,
1503
+	},
1504
+	{
1505
+		CLK_I2C1, "i2c1",
1506
+		i2c_parents, ARRAY_SIZE(i2c_parents),
1507
+		STM32F7_RCC_DCKCFGR2, 16, 3,
1508
+		STM32F4_RCC_APB1ENR, 21,
1509
+		CLK_SET_RATE_PARENT,
1510
+	},
1511
+	{
1512
+		CLK_I2C2, "i2c2",
1513
+		i2c_parents, ARRAY_SIZE(i2c_parents),
1514
+		STM32F7_RCC_DCKCFGR2, 18, 3,
1515
+		STM32F4_RCC_APB1ENR, 22,
1516
+		CLK_SET_RATE_PARENT,
1517
+	},
1518
+	{
1519
+		CLK_I2C3, "i2c3",
1520
+		i2c_parents, ARRAY_SIZE(i2c_parents),
1521
+		STM32F7_RCC_DCKCFGR2, 20, 3,
1522
+		STM32F4_RCC_APB1ENR, 23,
1523
+		CLK_SET_RATE_PARENT,
1524
+	},
1525
+	{
1526
+		CLK_I2C4, "i2c4",
1527
+		i2c_parents, ARRAY_SIZE(i2c_parents),
1528
+		STM32F7_RCC_DCKCFGR2, 22, 3,
1529
+		STM32F4_RCC_APB1ENR, 24,
1530
+		CLK_SET_RATE_PARENT,
1531
+	},
1532
+	{
1533
+		CLK_LPTIMER, "lptim1",
1534
+		lptim_parent, ARRAY_SIZE(lptim_parent),
1535
+		STM32F7_RCC_DCKCFGR2, 24, 3,
1536
+		STM32F4_RCC_APB1ENR, 9,
1537
+		CLK_SET_RATE_PARENT
1538
+	},
1539
+	{
1540
+		CLK_F769_DSI, "dsi",
1541
+		dsi_parent, ARRAY_SIZE(dsi_parent),
1542
+		STM32F7_RCC_DCKCFGR2, 0, 1,
1543
+		STM32F4_RCC_APB2ENR, 27,
1544
+		CLK_SET_RATE_PARENT
1545
+	},
1546
+	{
1547
+		CLK_DFSDM1, "dfsdm1",
1548
+		dfsdm1_src, ARRAY_SIZE(dfsdm1_src),
1549
+		STM32F4_RCC_DCKCFGR, 25, 1,
1550
+		STM32F4_RCC_APB2ENR, 29,
1551
+		CLK_SET_RATE_PARENT
1552
+	},
1553
+	{
1554
+		CLK_ADFSDM1, "adfsdm1",
1555
+		adsfdm1_parent, ARRAY_SIZE(adsfdm1_parent),
1556
+		STM32F4_RCC_DCKCFGR, 26, 1,
1557
+		STM32F4_RCC_APB2ENR, 29,
1558
+		CLK_SET_RATE_PARENT
1559
+	},
1560
+};
1561
+
13161562 static const struct stm32f4_clk_data stm32f429_clk_data = {
13171563 	.end_primary	= END_PRIMARY_CLK,
13181564 	.gates_data	= stm32f429_gates,
....@@ -1343,6 +1589,16 @@
13431589 	.aux_clk_num	= ARRAY_SIZE(stm32f746_aux_clk),
13441590 };
13451591 
1592
+static const struct stm32f4_clk_data stm32f769_clk_data = {
1593
+	.end_primary	= END_PRIMARY_CLK_F7,
1594
+	.gates_data	= stm32f769_gates,
1595
+	.gates_map	= stm32f769_gate_map,
1596
+	.gates_num	= ARRAY_SIZE(stm32f769_gates),
1597
+	.pll_data	= stm32f469_pll,
1598
+	.aux_clk	= stm32f769_aux_clk,
1599
+	.aux_clk_num	= ARRAY_SIZE(stm32f769_aux_clk),
1600
+};
1601
+
13461602 static const struct of_device_id stm32f4_of_match[] = {
13471603 	{
13481604 		.compatible = "st,stm32f42xx-rcc",
....@@ -1355,6 +1611,10 @@
13551611 	{
13561612 		.compatible = "st,stm32f746-rcc",
13571613 		.data = &stm32f746_clk_data
1614
+	},
1615
+	{
1616
+		.compatible = "st,stm32f769-rcc",
1617
+		.data = &stm32f769_clk_data
13581618 	},
13591619 	{}
13601620 };
....@@ -1427,13 +1687,12 @@
14271687 	int n;
14281688 	const struct of_device_id *match;
14291689 	const struct stm32f4_clk_data *data;
1430
-	unsigned long pllcfgr;
1431
-	const char *pllsrc;
14321690 	unsigned long pllm;
1691
+	struct clk_hw *pll_src_hw;
14331692 
14341693 	base = of_iomap(np, 0);
14351694 	if (!base) {
1436
-		pr_err("%s: unable to map resource\n", np->name);
1695
+		pr_err("%pOFn: unable to map resource\n", np);
14371696 		return;
14381697 	}
14391698 
....@@ -1460,21 +1719,33 @@
14601719 
14611720 	hse_clk = of_clk_get_parent_name(np, 0);
14621721 	dsi_parent[0] = hse_clk;
1722
+	pllsrc_parent[1] = hse_clk;
14631723 
14641724 	i2s_in_clk = of_clk_get_parent_name(np, 1);
14651725 
14661726 	i2s_parents[1] = i2s_in_clk;
14671727 	sai_parents[2] = i2s_in_clk;
14681728 
1729
+	if (of_device_is_compatible(np, "st,stm32f769-rcc")) {
1730
+		clk_hw_register_gate(NULL, "dfsdm1_apb", "apb2_div", 0,
1731
+				     base + STM32F4_RCC_APB2ENR, 29,
1732
+				     CLK_IGNORE_UNUSED, &stm32f4_clk_lock);
1733
+		dsi_parent[0] = pll_src;
1734
+		sai_parents[3] = pll_src;
1735
+	}
1736
+
14691737 	clks[CLK_HSI] = clk_hw_register_fixed_rate_with_accuracy(NULL, "hsi",
14701738 			NULL, 0, 16000000, 160000);
14711739 
1472
-	pllcfgr = readl(base + STM32F4_RCC_PLLCFGR);
1473
-	pllsrc = pllcfgr & BIT(22) ? hse_clk : "hsi";
1474
-	pllm = pllcfgr & 0x3f;
1740
+	pll_src_hw = clk_hw_register_mux(NULL, pll_src, pllsrc_parent,
1741
+					 ARRAY_SIZE(pllsrc_parent), 0,
1742
+					 base + STM32F4_RCC_PLLCFGR, 22, 1, 0,
1743
+					 &stm32f4_clk_lock);
14751744 
1476
-	clk_hw_register_fixed_factor(NULL, "vco_in", pllsrc,
1477
-					       0, 1, pllm);
1745
+	pllm = readl(base + STM32F4_RCC_PLLCFGR) & 0x3f;
1746
+
1747
+	clk_hw_register_fixed_factor(NULL, "vco_in", pll_src,
1748
+				     0, 1, pllm);
14781749 
14791750 	stm32f4_rcc_register_pll("vco_in", &data->pll_data[0],
14801751 			&stm32f4_clk_lock);
....@@ -1612,12 +1883,16 @@
16121883 			clks[aux_clk->idx] = hw;
16131884 	}
16141885 
1615
-	if (of_device_is_compatible(np, "st,stm32f746-rcc"))
1886
+	if (of_device_is_compatible(np, "st,stm32f746-rcc")) {
16161887 
16171888 		clk_hw_register_fixed_factor(NULL, "hsi_div488", "hsi", 0,
16181889 				1, 488);
16191890 
1891
+		clks[CLK_PLL_SRC] = pll_src_hw;
1892
+	}
1893
+
16201894 	of_clk_add_hw_provider(np, stm32f4_rcc_lookup_clk, NULL);
1895
+
16211896 	return;
16221897 fail:
16231898 	kfree(clks);
....@@ -1626,3 +1901,4 @@
16261901 CLK_OF_DECLARE_DRIVER(stm32f42xx_rcc, "st,stm32f42xx-rcc", stm32f4_rcc_init);
16271902 CLK_OF_DECLARE_DRIVER(stm32f46xx_rcc, "st,stm32f469-rcc", stm32f4_rcc_init);
16281903 CLK_OF_DECLARE_DRIVER(stm32f746_rcc, "st,stm32f746-rcc", stm32f4_rcc_init);
1904
+CLK_OF_DECLARE_DRIVER(stm32f769_rcc, "st,stm32f769-rcc", stm32f4_rcc_init);