add new system file

hc

2024-02-20 102a0743326a03cd1a1202ceda21e175b7d3575c

 kernel/drivers/clk/clk-pwm.c
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@@ -1,9 +1,6 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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 /*
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  * Copyright (C) 2014 Philipp Zabel, Pengutronix
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License version 2 as
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- * published by the Free Software Foundation.
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  *
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  * PWM (mis)used as clock output
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  */
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@@ -47,16 +44,30 @@
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 	return clk_pwm->fixed_rate;
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 }
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+static int clk_pwm_get_duty_cycle(struct clk_hw *hw, struct clk_duty *duty)
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+{
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+	struct clk_pwm *clk_pwm = to_clk_pwm(hw);
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+	struct pwm_state state;
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+
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+	pwm_get_state(clk_pwm->pwm, &state);
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+
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+	duty->num = state.duty_cycle;
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+	duty->den = state.period;
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+
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+	return 0;
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+}
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+
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 static const struct clk_ops clk_pwm_ops = {
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 	.prepare = clk_pwm_prepare,
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 	.unprepare = clk_pwm_unprepare,
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 	.recalc_rate = clk_pwm_recalc_rate,
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+	.get_duty_cycle = clk_pwm_get_duty_cycle,
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 };
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 static int clk_pwm_probe(struct platform_device *pdev)
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 {
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 	struct device_node *node = pdev->dev.of_node;
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-	struct clk_init_data init = {};
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+	struct clk_init_data init;
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 	struct clk_pwm *clk_pwm;
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 	struct pwm_device *pwm;
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 	struct pwm_args pargs;
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@@ -80,6 +91,11 @@
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 	if (of_property_read_u32(node, "clock-frequency", &clk_pwm->fixed_rate))
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 		clk_pwm->fixed_rate = div64_u64(NSEC_PER_SEC, pargs.period);
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+	if (!clk_pwm->fixed_rate) {
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+		dev_err(&pdev->dev, "fixed_rate cannot be zero\n");
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+		return -EINVAL;
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+	}
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+
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 	if (pargs.period != NSEC_PER_SEC / clk_pwm->fixed_rate &&
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 	    pargs.period != DIV_ROUND_UP(NSEC_PER_SEC, clk_pwm->fixed_rate)) {
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 		dev_err(&pdev->dev,
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@@ -101,7 +117,7 @@
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 	init.name = clk_name;
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 	init.ops = &clk_pwm_ops;
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-	init.flags = CLK_IS_BASIC;
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+	init.flags = 0;
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 	init.num_parents = 0;
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 	clk_pwm->pwm = pwm;