hc
2024-02-20 102a0743326a03cd1a1202ceda21e175b7d3575c
kernel/drivers/clk/clk-mux.c
....@@ -1,11 +1,8 @@
1
+// SPDX-License-Identifier: GPL-2.0
12 /*
23 * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
34 * Copyright (C) 2011 Richard Zhao, Linaro <richard.zhao@linaro.org>
45 * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
5
- *
6
- * This program is free software; you can redistribute it and/or modify
7
- * it under the terms of the GNU General Public License version 2 as
8
- * published by the Free Software Foundation.
96 *
107 * Simple multiplexer clock implementation
118 */
....@@ -25,6 +22,22 @@
2522 * rate - rate is only affected by parent switching. No clk_set_rate support
2623 * parent - parent is adjustable through clk_set_parent
2724 */
25
+
26
+static inline u32 clk_mux_readl(struct clk_mux *mux)
27
+{
28
+ if (mux->flags & CLK_MUX_BIG_ENDIAN)
29
+ return ioread32be(mux->reg);
30
+
31
+ return readl(mux->reg);
32
+}
33
+
34
+static inline void clk_mux_writel(struct clk_mux *mux, u32 val)
35
+{
36
+ if (mux->flags & CLK_MUX_BIG_ENDIAN)
37
+ iowrite32be(val, mux->reg);
38
+ else
39
+ writel(val, mux->reg);
40
+}
2841
2942 int clk_mux_val_to_index(struct clk_hw *hw, u32 *table, unsigned int flags,
3043 unsigned int val)
....@@ -76,7 +89,7 @@
7689 struct clk_mux *mux = to_clk_mux(hw);
7790 u32 val;
7891
79
- val = clk_readl(mux->reg) >> mux->shift;
92
+ val = clk_mux_readl(mux) >> mux->shift;
8093 val &= mux->mask;
8194
8295 return clk_mux_val_to_index(hw, mux->table, mux->flags, val);
....@@ -97,12 +110,12 @@
97110 if (mux->flags & CLK_MUX_HIWORD_MASK) {
98111 reg = mux->mask << (mux->shift + 16);
99112 } else {
100
- reg = clk_readl(mux->reg);
113
+ reg = clk_mux_readl(mux);
101114 reg &= ~(mux->mask << mux->shift);
102115 }
103116 val = val << mux->shift;
104117 reg |= val;
105
- clk_writel(reg, mux->reg);
118
+ clk_mux_writel(mux, reg);
106119
107120 if (mux->lock)
108121 spin_unlock_irqrestore(mux->lock, flags);
....@@ -132,17 +145,19 @@
132145 };
133146 EXPORT_SYMBOL_GPL(clk_mux_ro_ops);
134147
135
-struct clk_hw *clk_hw_register_mux_table(struct device *dev, const char *name,
136
- const char * const *parent_names, u8 num_parents,
137
- unsigned long flags,
138
- void __iomem *reg, u8 shift, u32 mask,
148
+struct clk_hw *__clk_hw_register_mux(struct device *dev, struct device_node *np,
149
+ const char *name, u8 num_parents,
150
+ const char * const *parent_names,
151
+ const struct clk_hw **parent_hws,
152
+ const struct clk_parent_data *parent_data,
153
+ unsigned long flags, void __iomem *reg, u8 shift, u32 mask,
139154 u8 clk_mux_flags, u32 *table, spinlock_t *lock)
140155 {
141156 struct clk_mux *mux;
142157 struct clk_hw *hw;
143158 struct clk_init_data init = {};
144159 u8 width = 0;
145
- int ret;
160
+ int ret = -EINVAL;
146161
147162 if (clk_mux_flags & CLK_MUX_HIWORD_MASK) {
148163 width = fls(mask) - ffs(mask) + 1;
....@@ -162,8 +177,10 @@
162177 init.ops = &clk_mux_ro_ops;
163178 else
164179 init.ops = &clk_mux_ops;
165
- init.flags = flags | CLK_IS_BASIC;
180
+ init.flags = flags;
166181 init.parent_names = parent_names;
182
+ init.parent_data = parent_data;
183
+ init.parent_hws = parent_hws;
167184 init.num_parents = num_parents;
168185
169186 /* struct clk_mux assignments */
....@@ -176,7 +193,10 @@
176193 mux->hw.init = &init;
177194
178195 hw = &mux->hw;
179
- ret = clk_hw_register(dev, hw);
196
+ if (dev || !np)
197
+ ret = clk_hw_register(dev, hw);
198
+ else if (np)
199
+ ret = of_clk_hw_register(np, hw);
180200 if (ret) {
181201 kfree(mux);
182202 hw = ERR_PTR(ret);
....@@ -184,52 +204,23 @@
184204
185205 return hw;
186206 }
187
-EXPORT_SYMBOL_GPL(clk_hw_register_mux_table);
207
+EXPORT_SYMBOL_GPL(__clk_hw_register_mux);
188208
189209 struct clk *clk_register_mux_table(struct device *dev, const char *name,
190210 const char * const *parent_names, u8 num_parents,
191
- unsigned long flags,
192
- void __iomem *reg, u8 shift, u32 mask,
211
+ unsigned long flags, void __iomem *reg, u8 shift, u32 mask,
193212 u8 clk_mux_flags, u32 *table, spinlock_t *lock)
194213 {
195214 struct clk_hw *hw;
196215
197
- hw = clk_hw_register_mux_table(dev, name, parent_names, num_parents,
198
- flags, reg, shift, mask, clk_mux_flags,
199
- table, lock);
216
+ hw = clk_hw_register_mux_table(dev, name, parent_names,
217
+ num_parents, flags, reg, shift, mask,
218
+ clk_mux_flags, table, lock);
200219 if (IS_ERR(hw))
201220 return ERR_CAST(hw);
202221 return hw->clk;
203222 }
204223 EXPORT_SYMBOL_GPL(clk_register_mux_table);
205
-
206
-struct clk *clk_register_mux(struct device *dev, const char *name,
207
- const char * const *parent_names, u8 num_parents,
208
- unsigned long flags,
209
- void __iomem *reg, u8 shift, u8 width,
210
- u8 clk_mux_flags, spinlock_t *lock)
211
-{
212
- u32 mask = BIT(width) - 1;
213
-
214
- return clk_register_mux_table(dev, name, parent_names, num_parents,
215
- flags, reg, shift, mask, clk_mux_flags,
216
- NULL, lock);
217
-}
218
-EXPORT_SYMBOL_GPL(clk_register_mux);
219
-
220
-struct clk_hw *clk_hw_register_mux(struct device *dev, const char *name,
221
- const char * const *parent_names, u8 num_parents,
222
- unsigned long flags,
223
- void __iomem *reg, u8 shift, u8 width,
224
- u8 clk_mux_flags, spinlock_t *lock)
225
-{
226
- u32 mask = BIT(width) - 1;
227
-
228
- return clk_hw_register_mux_table(dev, name, parent_names, num_parents,
229
- flags, reg, shift, mask, clk_mux_flags,
230
- NULL, lock);
231
-}
232
-EXPORT_SYMBOL_GPL(clk_hw_register_mux);
233224
234225 void clk_unregister_mux(struct clk *clk)
235226 {