add new system file

hc

2024-02-20 102a0743326a03cd1a1202ceda21e175b7d3575c

 kernel/drivers/clk/clk-gate.c
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@@ -1,10 +1,7 @@
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+// SPDX-License-Identifier: GPL-2.0
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 /*
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  * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
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  * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License version 2 as
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- * published by the Free Software Foundation.
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  *
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  * Gated clock implementation
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  */
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@@ -30,6 +27,22 @@
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  * parent - fixed parent.  No clk_set_parent support
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  */
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+static inline u32 clk_gate_readl(struct clk_gate *gate)
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+{
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+	if (gate->flags & CLK_GATE_BIG_ENDIAN)
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+		return ioread32be(gate->reg);
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+
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+	return readl(gate->reg);
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+}
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+
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+static inline void clk_gate_writel(struct clk_gate *gate, u32 val)
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+{
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+	if (gate->flags & CLK_GATE_BIG_ENDIAN)
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+		iowrite32be(val, gate->reg);
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+	else
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+		writel(val, gate->reg);
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+}
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+
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 /*
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  * It works on following logic:
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  *
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@@ -47,7 +60,7 @@
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 {
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 	struct clk_gate *gate = to_clk_gate(hw);
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 	int set = gate->flags & CLK_GATE_SET_TO_DISABLE ? 1 : 0;
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-	unsigned long uninitialized_var(flags);
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+	unsigned long flags;
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 	u32 reg;
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 	if (clk_always_on && !enable)
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@@ -65,7 +78,7 @@
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 		if (set)
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 			reg |= BIT(gate->bit_idx);
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 	} else {
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-		reg = clk_readl(gate->reg);
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+		reg = clk_gate_readl(gate);
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 		if (set)
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 			reg |= BIT(gate->bit_idx);
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@@ -73,7 +86,7 @@
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 			reg &= ~BIT(gate->bit_idx);
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 	}
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-	clk_writel(reg, gate->reg);
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+	clk_gate_writel(gate, reg);
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 	if (gate->lock)
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 		spin_unlock_irqrestore(gate->lock, flags);
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@@ -98,7 +111,7 @@
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 	u32 reg;
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 	struct clk_gate *gate = to_clk_gate(hw);
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-	reg = clk_readl(gate->reg);
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+	reg = clk_gate_readl(gate);
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 	/* if a set bit disables this clk, flip it before masking */
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 	if (gate->flags & CLK_GATE_SET_TO_DISABLE)
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@@ -117,26 +130,18 @@
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 };
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 EXPORT_SYMBOL_GPL(clk_gate_ops);
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-/**
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- * clk_hw_register_gate - register a gate clock with the clock framework
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- * @dev: device that is registering this clock
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- * @name: name of this clock
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- * @parent_name: name of this clock's parent
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- * @flags: framework-specific flags for this clock
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- * @reg: register address to control gating of this clock
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- * @bit_idx: which bit in the register controls gating of this clock
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- * @clk_gate_flags: gate-specific flags for this clock
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- * @lock: shared register lock for this clock
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- */
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-struct clk_hw *clk_hw_register_gate(struct device *dev, const char *name,
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-		const char *parent_name, unsigned long flags,
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+struct clk_hw *__clk_hw_register_gate(struct device *dev,
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+		struct device_node *np, const char *name,
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+		const char *parent_name, const struct clk_hw *parent_hw,
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+		const struct clk_parent_data *parent_data,
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+		unsigned long flags,
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 		void __iomem *reg, u8 bit_idx,
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 		u8 clk_gate_flags, spinlock_t *lock)
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 {
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 	struct clk_gate *gate;
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 	struct clk_hw *hw;
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 	struct clk_init_data init = {};
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-	int ret;
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+	int ret = -EINVAL;
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 	if (clk_gate_flags & CLK_GATE_HIWORD_MASK) {
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 		if (bit_idx > 15) {
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@@ -152,9 +157,14 @@
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 	init.name = name;
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 	init.ops = &clk_gate_ops;
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-	init.flags = flags | CLK_IS_BASIC;
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+	init.flags = flags;
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 	init.parent_names = parent_name ? &parent_name : NULL;
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-	init.num_parents = parent_name ? 1 : 0;
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+	init.parent_hws = parent_hw ? &parent_hw : NULL;
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+	init.parent_data = parent_data;
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+	if (parent_name || parent_hw || parent_data)
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+		init.num_parents = 1;
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+	else
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+		init.num_parents = 0;
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 	/* struct clk_gate assignments */
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 	gate->reg = reg;
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@@ -164,15 +174,19 @@
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 	gate->hw.init = &init;
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 	hw = &gate->hw;
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-	ret = clk_hw_register(dev, hw);
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+	if (dev || !np)
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+		ret = clk_hw_register(dev, hw);
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+	else if (np)
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+		ret = of_clk_hw_register(np, hw);
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 	if (ret) {
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 		kfree(gate);
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 		hw = ERR_PTR(ret);
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 	}
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 	return hw;
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+
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 }
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-EXPORT_SYMBOL_GPL(clk_hw_register_gate);
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+EXPORT_SYMBOL_GPL(__clk_hw_register_gate);
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 struct clk *clk_register_gate(struct device *dev, const char *name,
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 		const char *parent_name, unsigned long flags,