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2024-02-20 102a0743326a03cd1a1202ceda21e175b7d3575c 
 kernel/drivers/ata/ahci.h
....@@ -1,3 +1,4 @@
1
+/* SPDX-License-Identifier: GPL-2.0-or-later */
12 /*
23  *  ahci.h - Common AHCI SATA definitions and declarations
34  *
....@@ -7,29 +8,12 @@
78  *
89  *  Copyright 2004-2005 Red Hat, Inc.
910  *
10
- *
11
- *  This program is free software; you can redistribute it and/or modify
12
- *  it under the terms of the GNU General Public License as published by
13
- *  the Free Software Foundation; either version 2, or (at your option)
14
- *  any later version.
15
- *
16
- *  This program is distributed in the hope that it will be useful,
17
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
18
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
19
- *  GNU General Public License for more details.
20
- *
21
- *  You should have received a copy of the GNU General Public License
22
- *  along with this program; see the file COPYING.  If not, write to
23
- *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24
- *
25
- *
2611  * libata documentation is available via 'make {ps|pdf}docs',
2712  * as Documentation/driver-api/libata.rst
2813  *
2914  * AHCI hardware documentation:
3015  * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
3116  * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
32
- *
3317  */
3418 
3519 #ifndef _AHCI_H
....@@ -40,6 +24,7 @@
4024 #include <linux/libata.h>
4125 #include <linux/phy/phy.h>
4226 #include <linux/regulator/consumer.h>
27
+#include <linux/bits.h>
4328 
4429 /* Enclosure Management Control */
4530 #define EM_CTRL_MSG_TYPE              0x000f0000
....@@ -70,12 +55,12 @@
7055 	AHCI_PORT_PRIV_FBS_DMA_SZ	= AHCI_CMD_SLOT_SZ +
7156 					  AHCI_CMD_TBL_AR_SZ +
7257 					  (AHCI_RX_FIS_SZ * 16),
73
-	AHCI_IRQ_ON_SG		= (1 << 31),
74
-	AHCI_CMD_ATAPI		= (1 << 5),
75
-	AHCI_CMD_WRITE		= (1 << 6),
76
-	AHCI_CMD_PREFETCH	= (1 << 7),
77
-	AHCI_CMD_RESET		= (1 << 8),
78
-	AHCI_CMD_CLR_BUSY	= (1 << 10),
58
+	AHCI_IRQ_ON_SG		= BIT(31),
59
+	AHCI_CMD_ATAPI		= BIT(5),
60
+	AHCI_CMD_WRITE		= BIT(6),
61
+	AHCI_CMD_PREFETCH	= BIT(7),
62
+	AHCI_CMD_RESET		= BIT(8),
63
+	AHCI_CMD_CLR_BUSY	= BIT(10),
7964 
8065 	RX_FIS_PIO_SETUP	= 0x20,	/* offset of PIO Setup FIS data */
8166 	RX_FIS_D2H_REG		= 0x40,	/* offset of D2H Register FIS data */
....@@ -93,37 +78,37 @@
9378 	HOST_CAP2		= 0x24, /* host capabilities, extended */
9479 
9580 	/* HOST_CTL bits */
96
-	HOST_RESET		= (1 << 0),  /* reset controller; self-clear */
97
-	HOST_IRQ_EN		= (1 << 1),  /* global IRQ enable */
98
-	HOST_MRSM		= (1 << 2),  /* MSI Revert to Single Message */
99
-	HOST_AHCI_EN		= (1 << 31), /* AHCI enabled */
81
+	HOST_RESET		= BIT(0),  /* reset controller; self-clear */
82
+	HOST_IRQ_EN		= BIT(1),  /* global IRQ enable */
83
+	HOST_MRSM		= BIT(2),  /* MSI Revert to Single Message */
84
+	HOST_AHCI_EN		= BIT(31), /* AHCI enabled */
10085 
10186 	/* HOST_CAP bits */
102
-	HOST_CAP_SXS		= (1 << 5),  /* Supports External SATA */
103
-	HOST_CAP_EMS		= (1 << 6),  /* Enclosure Management support */
104
-	HOST_CAP_CCC		= (1 << 7),  /* Command Completion Coalescing */
105
-	HOST_CAP_PART		= (1 << 13), /* Partial state capable */
106
-	HOST_CAP_SSC		= (1 << 14), /* Slumber state capable */
107
-	HOST_CAP_PIO_MULTI	= (1 << 15), /* PIO multiple DRQ support */
108
-	HOST_CAP_FBS		= (1 << 16), /* FIS-based switching support */
109
-	HOST_CAP_PMP		= (1 << 17), /* Port Multiplier support */
110
-	HOST_CAP_ONLY		= (1 << 18), /* Supports AHCI mode only */
111
-	HOST_CAP_CLO		= (1 << 24), /* Command List Override support */
112
-	HOST_CAP_LED		= (1 << 25), /* Supports activity LED */
113
-	HOST_CAP_ALPM		= (1 << 26), /* Aggressive Link PM support */
114
-	HOST_CAP_SSS		= (1 << 27), /* Staggered Spin-up */
115
-	HOST_CAP_MPS		= (1 << 28), /* Mechanical presence switch */
116
-	HOST_CAP_SNTF		= (1 << 29), /* SNotification register */
117
-	HOST_CAP_NCQ		= (1 << 30), /* Native Command Queueing */
118
-	HOST_CAP_64		= (1 << 31), /* PCI DAC (64-bit DMA) support */
87
+	HOST_CAP_SXS		= BIT(5),  /* Supports External SATA */
88
+	HOST_CAP_EMS		= BIT(6),  /* Enclosure Management support */
89
+	HOST_CAP_CCC		= BIT(7),  /* Command Completion Coalescing */
90
+	HOST_CAP_PART		= BIT(13), /* Partial state capable */
91
+	HOST_CAP_SSC		= BIT(14), /* Slumber state capable */
92
+	HOST_CAP_PIO_MULTI	= BIT(15), /* PIO multiple DRQ support */
93
+	HOST_CAP_FBS		= BIT(16), /* FIS-based switching support */
94
+	HOST_CAP_PMP		= BIT(17), /* Port Multiplier support */
95
+	HOST_CAP_ONLY		= BIT(18), /* Supports AHCI mode only */
96
+	HOST_CAP_CLO		= BIT(24), /* Command List Override support */
97
+	HOST_CAP_LED		= BIT(25), /* Supports activity LED */
98
+	HOST_CAP_ALPM		= BIT(26), /* Aggressive Link PM support */
99
+	HOST_CAP_SSS		= BIT(27), /* Staggered Spin-up */
100
+	HOST_CAP_MPS		= BIT(28), /* Mechanical presence switch */
101
+	HOST_CAP_SNTF		= BIT(29), /* SNotification register */
102
+	HOST_CAP_NCQ		= BIT(30), /* Native Command Queueing */
103
+	HOST_CAP_64		= BIT(31), /* PCI DAC (64-bit DMA) support */
119104 
120105 	/* HOST_CAP2 bits */
121
-	HOST_CAP2_BOH		= (1 << 0),  /* BIOS/OS handoff supported */
122
-	HOST_CAP2_NVMHCI	= (1 << 1),  /* NVMHCI supported */
123
-	HOST_CAP2_APST		= (1 << 2),  /* Automatic partial to slumber */
124
-	HOST_CAP2_SDS		= (1 << 3),  /* Support device sleep */
125
-	HOST_CAP2_SADM		= (1 << 4),  /* Support aggressive DevSlp */
126
-	HOST_CAP2_DESO		= (1 << 5),  /* DevSlp from slumber only */
106
+	HOST_CAP2_BOH		= BIT(0),  /* BIOS/OS handoff supported */
107
+	HOST_CAP2_NVMHCI	= BIT(1),  /* NVMHCI supported */
108
+	HOST_CAP2_APST		= BIT(2),  /* Automatic partial to slumber */
109
+	HOST_CAP2_SDS		= BIT(3),  /* Support device sleep */
110
+	HOST_CAP2_SADM		= BIT(4),  /* Support aggressive DevSlp */
111
+	HOST_CAP2_DESO		= BIT(5),  /* DevSlp from slumber only */
127112 
128113 	/* registers for each SATA port */
129114 	PORT_LST_ADDR		= 0x00, /* command list DMA addr */
....@@ -145,24 +130,24 @@
145130 	PORT_DEVSLP		= 0x44, /* device sleep */
146131 
147132 	/* PORT_IRQ_{STAT,MASK} bits */
148
-	PORT_IRQ_COLD_PRES	= (1 << 31), /* cold presence detect */
149
-	PORT_IRQ_TF_ERR		= (1 << 30), /* task file error */
150
-	PORT_IRQ_HBUS_ERR	= (1 << 29), /* host bus fatal error */
151
-	PORT_IRQ_HBUS_DATA_ERR	= (1 << 28), /* host bus data error */
152
-	PORT_IRQ_IF_ERR		= (1 << 27), /* interface fatal error */
153
-	PORT_IRQ_IF_NONFATAL	= (1 << 26), /* interface non-fatal error */
154
-	PORT_IRQ_OVERFLOW	= (1 << 24), /* xfer exhausted available S/G */
155
-	PORT_IRQ_BAD_PMP	= (1 << 23), /* incorrect port multiplier */
133
+	PORT_IRQ_COLD_PRES	= BIT(31), /* cold presence detect */
134
+	PORT_IRQ_TF_ERR		= BIT(30), /* task file error */
135
+	PORT_IRQ_HBUS_ERR	= BIT(29), /* host bus fatal error */
136
+	PORT_IRQ_HBUS_DATA_ERR	= BIT(28), /* host bus data error */
137
+	PORT_IRQ_IF_ERR		= BIT(27), /* interface fatal error */
138
+	PORT_IRQ_IF_NONFATAL	= BIT(26), /* interface non-fatal error */
139
+	PORT_IRQ_OVERFLOW	= BIT(24), /* xfer exhausted available S/G */
140
+	PORT_IRQ_BAD_PMP	= BIT(23), /* incorrect port multiplier */
156141 
157
-	PORT_IRQ_PHYRDY		= (1 << 22), /* PhyRdy changed */
158
-	PORT_IRQ_DEV_ILCK	= (1 << 7), /* device interlock */
159
-	PORT_IRQ_CONNECT	= (1 << 6), /* port connect change status */
160
-	PORT_IRQ_SG_DONE	= (1 << 5), /* descriptor processed */
161
-	PORT_IRQ_UNK_FIS	= (1 << 4), /* unknown FIS rx'd */
162
-	PORT_IRQ_SDB_FIS	= (1 << 3), /* Set Device Bits FIS rx'd */
163
-	PORT_IRQ_DMAS_FIS	= (1 << 2), /* DMA Setup FIS rx'd */
164
-	PORT_IRQ_PIOS_FIS	= (1 << 1), /* PIO Setup FIS rx'd */
165
-	PORT_IRQ_D2H_REG_FIS	= (1 << 0), /* D2H Register FIS rx'd */
142
+	PORT_IRQ_PHYRDY		= BIT(22), /* PhyRdy changed */
143
+	PORT_IRQ_DEV_ILCK	= BIT(7),  /* device interlock */
144
+	PORT_IRQ_CONNECT	= BIT(6),  /* port connect change status */
145
+	PORT_IRQ_SG_DONE	= BIT(5),  /* descriptor processed */
146
+	PORT_IRQ_UNK_FIS	= BIT(4),  /* unknown FIS rx'd */
147
+	PORT_IRQ_SDB_FIS	= BIT(3),  /* Set Device Bits FIS rx'd */
148
+	PORT_IRQ_DMAS_FIS	= BIT(2),  /* DMA Setup FIS rx'd */
149
+	PORT_IRQ_PIOS_FIS	= BIT(1),  /* PIO Setup FIS rx'd */
150
+	PORT_IRQ_D2H_REG_FIS	= BIT(0),  /* D2H Register FIS rx'd */
166151 
167152 	PORT_IRQ_FREEZE		= PORT_IRQ_HBUS_ERR |
168153 				  PORT_IRQ_IF_ERR |
....@@ -178,34 +163,34 @@
178163 				  PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
179164 
180165 	/* PORT_CMD bits */
181
-	PORT_CMD_ASP		= (1 << 27), /* Aggressive Slumber/Partial */
182
-	PORT_CMD_ALPE		= (1 << 26), /* Aggressive Link PM enable */
183
-	PORT_CMD_ATAPI		= (1 << 24), /* Device is ATAPI */
184
-	PORT_CMD_FBSCP		= (1 << 22), /* FBS Capable Port */
185
-	PORT_CMD_ESP		= (1 << 21), /* External Sata Port */
186
-	PORT_CMD_HPCP		= (1 << 18), /* HotPlug Capable Port */
187
-	PORT_CMD_PMP		= (1 << 17), /* PMP attached */
188
-	PORT_CMD_LIST_ON	= (1 << 15), /* cmd list DMA engine running */
189
-	PORT_CMD_FIS_ON		= (1 << 14), /* FIS DMA engine running */
190
-	PORT_CMD_FIS_RX		= (1 << 4), /* Enable FIS receive DMA engine */
191
-	PORT_CMD_CLO		= (1 << 3), /* Command list override */
192
-	PORT_CMD_POWER_ON	= (1 << 2), /* Power up device */
193
-	PORT_CMD_SPIN_UP	= (1 << 1), /* Spin up device */
194
-	PORT_CMD_START		= (1 << 0), /* Enable port DMA engine */
166
+	PORT_CMD_ASP		= BIT(27), /* Aggressive Slumber/Partial */
167
+	PORT_CMD_ALPE		= BIT(26), /* Aggressive Link PM enable */
168
+	PORT_CMD_ATAPI		= BIT(24), /* Device is ATAPI */
169
+	PORT_CMD_FBSCP		= BIT(22), /* FBS Capable Port */
170
+	PORT_CMD_ESP		= BIT(21), /* External Sata Port */
171
+	PORT_CMD_HPCP		= BIT(18), /* HotPlug Capable Port */
172
+	PORT_CMD_PMP		= BIT(17), /* PMP attached */
173
+	PORT_CMD_LIST_ON	= BIT(15), /* cmd list DMA engine running */
174
+	PORT_CMD_FIS_ON		= BIT(14), /* FIS DMA engine running */
175
+	PORT_CMD_FIS_RX		= BIT(4),  /* Enable FIS receive DMA engine */
176
+	PORT_CMD_CLO		= BIT(3),  /* Command list override */
177
+	PORT_CMD_POWER_ON	= BIT(2),  /* Power up device */
178
+	PORT_CMD_SPIN_UP	= BIT(1),  /* Spin up device */
179
+	PORT_CMD_START		= BIT(0),  /* Enable port DMA engine */
195180 
196
-	PORT_CMD_ICC_MASK	= (0xf << 28), /* i/f ICC state mask */
197
-	PORT_CMD_ICC_ACTIVE	= (0x1 << 28), /* Put i/f in active state */
198
-	PORT_CMD_ICC_PARTIAL	= (0x2 << 28), /* Put i/f in partial state */
199
-	PORT_CMD_ICC_SLUMBER	= (0x6 << 28), /* Put i/f in slumber state */
181
+	PORT_CMD_ICC_MASK	= (0xfu << 28), /* i/f ICC state mask */
182
+	PORT_CMD_ICC_ACTIVE	= (0x1u << 28), /* Put i/f in active state */
183
+	PORT_CMD_ICC_PARTIAL	= (0x2u << 28), /* Put i/f in partial state */
184
+	PORT_CMD_ICC_SLUMBER	= (0x6u << 28), /* Put i/f in slumber state */
200185 
201186 	/* PORT_FBS bits */
202187 	PORT_FBS_DWE_OFFSET	= 16, /* FBS device with error offset */
203188 	PORT_FBS_ADO_OFFSET	= 12, /* FBS active dev optimization offset */
204189 	PORT_FBS_DEV_OFFSET	= 8,  /* FBS device to issue offset */
205190 	PORT_FBS_DEV_MASK	= (0xf << PORT_FBS_DEV_OFFSET),  /* FBS.DEV */
206
-	PORT_FBS_SDE		= (1 << 2), /* FBS single device error */
207
-	PORT_FBS_DEC		= (1 << 1), /* FBS device error clear */
208
-	PORT_FBS_EN		= (1 << 0), /* Enable FBS */
191
+	PORT_FBS_SDE		= BIT(2), /* FBS single device error */
192
+	PORT_FBS_DEC		= BIT(1), /* FBS device error clear */
193
+	PORT_FBS_EN		= BIT(0), /* Enable FBS */
209194 
210195 	/* PORT_DEVSLP bits */
211196 	PORT_DEVSLP_DM_OFFSET	= 25,             /* DITO multiplier offset */
....@@ -213,47 +198,52 @@
213198 	PORT_DEVSLP_DITO_OFFSET	= 15,             /* DITO offset */
214199 	PORT_DEVSLP_MDAT_OFFSET	= 10,             /* Minimum assertion time */
215200 	PORT_DEVSLP_DETO_OFFSET	= 2,              /* DevSlp exit timeout */
216
-	PORT_DEVSLP_DSP		= (1 << 1),       /* DevSlp present */
217
-	PORT_DEVSLP_ADSE	= (1 << 0),       /* Aggressive DevSlp enable */
201
+	PORT_DEVSLP_DSP		= BIT(1),         /* DevSlp present */
202
+	PORT_DEVSLP_ADSE	= BIT(0),         /* Aggressive DevSlp enable */
218203 
219204 	/* hpriv->flags bits */
220205 
221206 #define AHCI_HFLAGS(flags)		.private_data	= (void *)(flags)
222207 
223
-	AHCI_HFLAG_NO_NCQ		= (1 << 0),
224
-	AHCI_HFLAG_IGN_IRQ_IF_ERR	= (1 << 1), /* ignore IRQ_IF_ERR */
225
-	AHCI_HFLAG_IGN_SERR_INTERNAL	= (1 << 2), /* ignore SERR_INTERNAL */
226
-	AHCI_HFLAG_32BIT_ONLY		= (1 << 3), /* force 32bit */
227
-	AHCI_HFLAG_MV_PATA		= (1 << 4), /* PATA port */
228
-	AHCI_HFLAG_NO_MSI		= (1 << 5), /* no PCI MSI */
229
-	AHCI_HFLAG_NO_PMP		= (1 << 6), /* no PMP */
230
-	AHCI_HFLAG_SECT255		= (1 << 8), /* max 255 sectors */
231
-	AHCI_HFLAG_YES_NCQ		= (1 << 9), /* force NCQ cap on */
232
-	AHCI_HFLAG_NO_SUSPEND		= (1 << 10), /* don't suspend */
233
-	AHCI_HFLAG_SRST_TOUT_IS_OFFLINE	= (1 << 11), /* treat SRST timeout as
234
-							link offline */
235
-	AHCI_HFLAG_NO_SNTF		= (1 << 12), /* no sntf */
236
-	AHCI_HFLAG_NO_FPDMA_AA		= (1 << 13), /* no FPDMA AA */
237
-	AHCI_HFLAG_YES_FBS		= (1 << 14), /* force FBS cap on */
238
-	AHCI_HFLAG_DELAY_ENGINE		= (1 << 15), /* do not start engine on
239
-						        port start (wait until
240
-						        error-handling stage) */
241
-	AHCI_HFLAG_NO_DEVSLP		= (1 << 17), /* no device sleep */
242
-	AHCI_HFLAG_NO_FBS		= (1 << 18), /* no FBS */
208
+	AHCI_HFLAG_NO_NCQ		= BIT(0),
209
+	AHCI_HFLAG_IGN_IRQ_IF_ERR	= BIT(1), /* ignore IRQ_IF_ERR */
210
+	AHCI_HFLAG_IGN_SERR_INTERNAL	= BIT(2), /* ignore SERR_INTERNAL */
211
+	AHCI_HFLAG_32BIT_ONLY		= BIT(3), /* force 32bit */
212
+	AHCI_HFLAG_MV_PATA		= BIT(4), /* PATA port */
213
+	AHCI_HFLAG_NO_MSI		= BIT(5), /* no PCI MSI */
214
+	AHCI_HFLAG_NO_PMP		= BIT(6), /* no PMP */
215
+	AHCI_HFLAG_SECT255		= BIT(8), /* max 255 sectors */
216
+	AHCI_HFLAG_YES_NCQ		= BIT(9), /* force NCQ cap on */
217
+	AHCI_HFLAG_NO_SUSPEND		= BIT(10), /* don't suspend */
218
+	AHCI_HFLAG_SRST_TOUT_IS_OFFLINE	= BIT(11), /* treat SRST timeout as
219
+						      link offline */
220
+	AHCI_HFLAG_NO_SNTF		= BIT(12), /* no sntf */
221
+	AHCI_HFLAG_NO_FPDMA_AA		= BIT(13), /* no FPDMA AA */
222
+	AHCI_HFLAG_YES_FBS		= BIT(14), /* force FBS cap on */
223
+	AHCI_HFLAG_DELAY_ENGINE		= BIT(15), /* do not start engine on
224
+						      port start (wait until
225
+						      error-handling stage) */
226
+	AHCI_HFLAG_NO_DEVSLP		= BIT(17), /* no device sleep */
227
+	AHCI_HFLAG_NO_FBS		= BIT(18), /* no FBS */
243228 
244229 #ifdef CONFIG_PCI_MSI
245
-	AHCI_HFLAG_MULTI_MSI		= (1 << 20), /* per-port MSI(-X) */
230
+	AHCI_HFLAG_MULTI_MSI		= BIT(20), /* per-port MSI(-X) */
246231 #else
247232 	/* compile out MSI infrastructure */
248233 	AHCI_HFLAG_MULTI_MSI		= 0,
249234 #endif
250
-	AHCI_HFLAG_WAKE_BEFORE_STOP	= (1 << 22), /* wake before DMA stop */
251
-	AHCI_HFLAG_YES_ALPM		= (1 << 23), /* force ALPM cap on */
252
-	AHCI_HFLAG_NO_WRITE_TO_RO	= (1 << 24), /* don't write to read
253
-							only registers */
254
-	AHCI_HFLAG_IS_MOBILE		= (1 << 25), /* mobile chipset, use
255
-							SATA_MOBILE_LPM_POLICY
256
-							as default lpm_policy */
235
+	AHCI_HFLAG_WAKE_BEFORE_STOP	= BIT(22), /* wake before DMA stop */
236
+	AHCI_HFLAG_YES_ALPM		= BIT(23), /* force ALPM cap on */
237
+	AHCI_HFLAG_NO_WRITE_TO_RO	= BIT(24), /* don't write to read
238
+						      only registers */
239
+	AHCI_HFLAG_IS_MOBILE            = BIT(25), /* mobile chipset, use
240
+						      SATA_MOBILE_LPM_POLICY
241
+						      as default lpm_policy */
242
+	AHCI_HFLAG_SUSPEND_PHYS		= BIT(26), /* handle PHYs during
243
+						      suspend/resume */
244
+	AHCI_HFLAG_IGN_NOTSUPP_POWER_ON	= BIT(27), /* ignore -EOPNOTSUPP
245
+						      from phy_power_on() */
246
+	AHCI_HFLAG_NO_SXS		= BIT(28), /* SXS not supported */
257247 
258248 	/* ap->flags bits */
259249 
....@@ -265,26 +255,26 @@
265255 	PCS_7				= 0x94, /* 7+ port PCS (Denverton) */
266256 
267257 	/* em constants */
268
-	EM_MAX_SLOTS			= 8,
258
+	EM_MAX_SLOTS			= SATA_PMP_MAX_PORTS,
269259 	EM_MAX_RETRY			= 5,
270260 
271261 	/* em_ctl bits */
272
-	EM_CTL_RST		= (1 << 9), /* Reset */
273
-	EM_CTL_TM		= (1 << 8), /* Transmit Message */
274
-	EM_CTL_MR		= (1 << 0), /* Message Received */
275
-	EM_CTL_ALHD		= (1 << 26), /* Activity LED */
276
-	EM_CTL_XMT		= (1 << 25), /* Transmit Only */
277
-	EM_CTL_SMB		= (1 << 24), /* Single Message Buffer */
278
-	EM_CTL_SGPIO		= (1 << 19), /* SGPIO messages supported */
279
-	EM_CTL_SES		= (1 << 18), /* SES-2 messages supported */
280
-	EM_CTL_SAFTE		= (1 << 17), /* SAF-TE messages supported */
281
-	EM_CTL_LED		= (1 << 16), /* LED messages supported */
262
+	EM_CTL_RST		= BIT(9), /* Reset */
263
+	EM_CTL_TM		= BIT(8), /* Transmit Message */
264
+	EM_CTL_MR		= BIT(0), /* Message Received */
265
+	EM_CTL_ALHD		= BIT(26), /* Activity LED */
266
+	EM_CTL_XMT		= BIT(25), /* Transmit Only */
267
+	EM_CTL_SMB		= BIT(24), /* Single Message Buffer */
268
+	EM_CTL_SGPIO		= BIT(19), /* SGPIO messages supported */
269
+	EM_CTL_SES		= BIT(18), /* SES-2 messages supported */
270
+	EM_CTL_SAFTE		= BIT(17), /* SAF-TE messages supported */
271
+	EM_CTL_LED		= BIT(16), /* LED messages supported */
282272 
283273 	/* em message type */
284
-	EM_MSG_TYPE_LED		= (1 << 0), /* LED */
285
-	EM_MSG_TYPE_SAFTE	= (1 << 1), /* SAF-TE */
286
-	EM_MSG_TYPE_SES2	= (1 << 2), /* SES-2 */
287
-	EM_MSG_TYPE_SGPIO	= (1 << 3), /* SGPIO */
274
+	EM_MSG_TYPE_LED		= BIT(0), /* LED */
275
+	EM_MSG_TYPE_SAFTE	= BIT(1), /* SAF-TE */
276
+	EM_MSG_TYPE_SES2	= BIT(2), /* SES-2 */
277
+	EM_MSG_TYPE_SGPIO	= BIT(3), /* SGPIO */
288278 };
289279 
290280 struct ahci_cmd_hdr {
....@@ -350,10 +340,13 @@
350340 	u32 			em_loc; /* enclosure management location */
351341 	u32			em_buf_sz;	/* EM buffer size in byte */
352342 	u32			em_msg_type;	/* EM message type */
343
+	u32			remapped_nvme;	/* NVMe remapped device count */
353344 	bool			got_runtime_pm; /* Did we do pm_runtime_get? */
354345 	struct clk		*clks[AHCI_MAX_CLKS]; /* Optional */
355346 	struct reset_control	*rsts;		/* Optional */
356347 	struct regulator	**target_pwrs;	/* Optional */
348
+	struct regulator	*ahci_regulator;/* Optional */
349
+	struct regulator	*phy_regulator;/* Optional */
357350 	/*
358351 	 * If platform uses PHYs. There is a 1:1 relation between the port number and
359352 	 * the PHY position in this array.