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2024-02-20 102a0743326a03cd1a1202ceda21e175b7d3575c

 kernel/drivers/ata/ahci.h
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@@ -24,6 +24,7 @@
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 #include <linux/libata.h>
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 #include <linux/phy/phy.h>
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 #include <linux/regulator/consumer.h>
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+#include <linux/bits.h>
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 /* Enclosure Management Control */
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 #define EM_CTRL_MSG_TYPE              0x000f0000
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@@ -54,12 +55,12 @@
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 	AHCI_PORT_PRIV_FBS_DMA_SZ	= AHCI_CMD_SLOT_SZ +
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 					  AHCI_CMD_TBL_AR_SZ +
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 					  (AHCI_RX_FIS_SZ * 16),
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-	AHCI_IRQ_ON_SG		= (1 << 31),
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-	AHCI_CMD_ATAPI		= (1 << 5),
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-	AHCI_CMD_WRITE		= (1 << 6),
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-	AHCI_CMD_PREFETCH	= (1 << 7),
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-	AHCI_CMD_RESET		= (1 << 8),
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-	AHCI_CMD_CLR_BUSY	= (1 << 10),
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+	AHCI_IRQ_ON_SG		= BIT(31),
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+	AHCI_CMD_ATAPI		= BIT(5),
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+	AHCI_CMD_WRITE		= BIT(6),
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+	AHCI_CMD_PREFETCH	= BIT(7),
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+	AHCI_CMD_RESET		= BIT(8),
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+	AHCI_CMD_CLR_BUSY	= BIT(10),
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 	RX_FIS_PIO_SETUP	= 0x20,	/* offset of PIO Setup FIS data */
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 	RX_FIS_D2H_REG		= 0x40,	/* offset of D2H Register FIS data */
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@@ -77,37 +78,37 @@
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 	HOST_CAP2		= 0x24, /* host capabilities, extended */
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 	/* HOST_CTL bits */
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-	HOST_RESET		= (1 << 0),  /* reset controller; self-clear */
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-	HOST_IRQ_EN		= (1 << 1),  /* global IRQ enable */
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-	HOST_MRSM		= (1 << 2),  /* MSI Revert to Single Message */
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-	HOST_AHCI_EN		= (1 << 31), /* AHCI enabled */
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+	HOST_RESET		= BIT(0),  /* reset controller; self-clear */
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+	HOST_IRQ_EN		= BIT(1),  /* global IRQ enable */
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+	HOST_MRSM		= BIT(2),  /* MSI Revert to Single Message */
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+	HOST_AHCI_EN		= BIT(31), /* AHCI enabled */
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 	/* HOST_CAP bits */
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-	HOST_CAP_SXS		= (1 << 5),  /* Supports External SATA */
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-	HOST_CAP_EMS		= (1 << 6),  /* Enclosure Management support */
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-	HOST_CAP_CCC		= (1 << 7),  /* Command Completion Coalescing */
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-	HOST_CAP_PART		= (1 << 13), /* Partial state capable */
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-	HOST_CAP_SSC		= (1 << 14), /* Slumber state capable */
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-	HOST_CAP_PIO_MULTI	= (1 << 15), /* PIO multiple DRQ support */
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-	HOST_CAP_FBS		= (1 << 16), /* FIS-based switching support */
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-	HOST_CAP_PMP		= (1 << 17), /* Port Multiplier support */
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-	HOST_CAP_ONLY		= (1 << 18), /* Supports AHCI mode only */
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-	HOST_CAP_CLO		= (1 << 24), /* Command List Override support */
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-	HOST_CAP_LED		= (1 << 25), /* Supports activity LED */
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-	HOST_CAP_ALPM		= (1 << 26), /* Aggressive Link PM support */
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-	HOST_CAP_SSS		= (1 << 27), /* Staggered Spin-up */
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-	HOST_CAP_MPS		= (1 << 28), /* Mechanical presence switch */
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-	HOST_CAP_SNTF		= (1 << 29), /* SNotification register */
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-	HOST_CAP_NCQ		= (1 << 30), /* Native Command Queueing */
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-	HOST_CAP_64		= (1 << 31), /* PCI DAC (64-bit DMA) support */
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+	HOST_CAP_SXS		= BIT(5),  /* Supports External SATA */
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+	HOST_CAP_EMS		= BIT(6),  /* Enclosure Management support */
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+	HOST_CAP_CCC		= BIT(7),  /* Command Completion Coalescing */
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+	HOST_CAP_PART		= BIT(13), /* Partial state capable */
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+	HOST_CAP_SSC		= BIT(14), /* Slumber state capable */
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+	HOST_CAP_PIO_MULTI	= BIT(15), /* PIO multiple DRQ support */
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+	HOST_CAP_FBS		= BIT(16), /* FIS-based switching support */
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+	HOST_CAP_PMP		= BIT(17), /* Port Multiplier support */
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+	HOST_CAP_ONLY		= BIT(18), /* Supports AHCI mode only */
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+	HOST_CAP_CLO		= BIT(24), /* Command List Override support */
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+	HOST_CAP_LED		= BIT(25), /* Supports activity LED */
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+	HOST_CAP_ALPM		= BIT(26), /* Aggressive Link PM support */
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+	HOST_CAP_SSS		= BIT(27), /* Staggered Spin-up */
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+	HOST_CAP_MPS		= BIT(28), /* Mechanical presence switch */
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+	HOST_CAP_SNTF		= BIT(29), /* SNotification register */
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+	HOST_CAP_NCQ		= BIT(30), /* Native Command Queueing */
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+	HOST_CAP_64		= BIT(31), /* PCI DAC (64-bit DMA) support */
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 	/* HOST_CAP2 bits */
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-	HOST_CAP2_BOH		= (1 << 0),  /* BIOS/OS handoff supported */
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-	HOST_CAP2_NVMHCI	= (1 << 1),  /* NVMHCI supported */
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-	HOST_CAP2_APST		= (1 << 2),  /* Automatic partial to slumber */
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-	HOST_CAP2_SDS		= (1 << 3),  /* Support device sleep */
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-	HOST_CAP2_SADM		= (1 << 4),  /* Support aggressive DevSlp */
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-	HOST_CAP2_DESO		= (1 << 5),  /* DevSlp from slumber only */
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+	HOST_CAP2_BOH		= BIT(0),  /* BIOS/OS handoff supported */
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+	HOST_CAP2_NVMHCI	= BIT(1),  /* NVMHCI supported */
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+	HOST_CAP2_APST		= BIT(2),  /* Automatic partial to slumber */
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+	HOST_CAP2_SDS		= BIT(3),  /* Support device sleep */
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+	HOST_CAP2_SADM		= BIT(4),  /* Support aggressive DevSlp */
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+	HOST_CAP2_DESO		= BIT(5),  /* DevSlp from slumber only */
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 	/* registers for each SATA port */
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 	PORT_LST_ADDR		= 0x00, /* command list DMA addr */
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@@ -129,24 +130,24 @@
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 	PORT_DEVSLP		= 0x44, /* device sleep */
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 	/* PORT_IRQ_{STAT,MASK} bits */
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-	PORT_IRQ_COLD_PRES	= (1 << 31), /* cold presence detect */
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-	PORT_IRQ_TF_ERR		= (1 << 30), /* task file error */
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-	PORT_IRQ_HBUS_ERR	= (1 << 29), /* host bus fatal error */
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-	PORT_IRQ_HBUS_DATA_ERR	= (1 << 28), /* host bus data error */
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-	PORT_IRQ_IF_ERR		= (1 << 27), /* interface fatal error */
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-	PORT_IRQ_IF_NONFATAL	= (1 << 26), /* interface non-fatal error */
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-	PORT_IRQ_OVERFLOW	= (1 << 24), /* xfer exhausted available S/G */
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-	PORT_IRQ_BAD_PMP	= (1 << 23), /* incorrect port multiplier */
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+	PORT_IRQ_COLD_PRES	= BIT(31), /* cold presence detect */
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+	PORT_IRQ_TF_ERR		= BIT(30), /* task file error */
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+	PORT_IRQ_HBUS_ERR	= BIT(29), /* host bus fatal error */
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+	PORT_IRQ_HBUS_DATA_ERR	= BIT(28), /* host bus data error */
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+	PORT_IRQ_IF_ERR		= BIT(27), /* interface fatal error */
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+	PORT_IRQ_IF_NONFATAL	= BIT(26), /* interface non-fatal error */
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+	PORT_IRQ_OVERFLOW	= BIT(24), /* xfer exhausted available S/G */
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+	PORT_IRQ_BAD_PMP	= BIT(23), /* incorrect port multiplier */
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-	PORT_IRQ_PHYRDY		= (1 << 22), /* PhyRdy changed */
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-	PORT_IRQ_DEV_ILCK	= (1 << 7), /* device interlock */
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-	PORT_IRQ_CONNECT	= (1 << 6), /* port connect change status */
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-	PORT_IRQ_SG_DONE	= (1 << 5), /* descriptor processed */
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-	PORT_IRQ_UNK_FIS	= (1 << 4), /* unknown FIS rx'd */
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-	PORT_IRQ_SDB_FIS	= (1 << 3), /* Set Device Bits FIS rx'd */
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-	PORT_IRQ_DMAS_FIS	= (1 << 2), /* DMA Setup FIS rx'd */
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-	PORT_IRQ_PIOS_FIS	= (1 << 1), /* PIO Setup FIS rx'd */
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-	PORT_IRQ_D2H_REG_FIS	= (1 << 0), /* D2H Register FIS rx'd */
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+	PORT_IRQ_PHYRDY		= BIT(22), /* PhyRdy changed */
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+	PORT_IRQ_DEV_ILCK	= BIT(7),  /* device interlock */
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+	PORT_IRQ_CONNECT	= BIT(6),  /* port connect change status */
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+	PORT_IRQ_SG_DONE	= BIT(5),  /* descriptor processed */
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+	PORT_IRQ_UNK_FIS	= BIT(4),  /* unknown FIS rx'd */
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+	PORT_IRQ_SDB_FIS	= BIT(3),  /* Set Device Bits FIS rx'd */
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+	PORT_IRQ_DMAS_FIS	= BIT(2),  /* DMA Setup FIS rx'd */
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+	PORT_IRQ_PIOS_FIS	= BIT(1),  /* PIO Setup FIS rx'd */
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+	PORT_IRQ_D2H_REG_FIS	= BIT(0),  /* D2H Register FIS rx'd */
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 	PORT_IRQ_FREEZE		= PORT_IRQ_HBUS_ERR |
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 				  PORT_IRQ_IF_ERR |
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@@ -162,34 +163,34 @@
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 				  PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
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 	/* PORT_CMD bits */
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-	PORT_CMD_ASP		= (1 << 27), /* Aggressive Slumber/Partial */
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-	PORT_CMD_ALPE		= (1 << 26), /* Aggressive Link PM enable */
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-	PORT_CMD_ATAPI		= (1 << 24), /* Device is ATAPI */
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-	PORT_CMD_FBSCP		= (1 << 22), /* FBS Capable Port */
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-	PORT_CMD_ESP		= (1 << 21), /* External Sata Port */
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-	PORT_CMD_HPCP		= (1 << 18), /* HotPlug Capable Port */
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-	PORT_CMD_PMP		= (1 << 17), /* PMP attached */
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-	PORT_CMD_LIST_ON	= (1 << 15), /* cmd list DMA engine running */
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-	PORT_CMD_FIS_ON		= (1 << 14), /* FIS DMA engine running */
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-	PORT_CMD_FIS_RX		= (1 << 4), /* Enable FIS receive DMA engine */
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-	PORT_CMD_CLO		= (1 << 3), /* Command list override */
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-	PORT_CMD_POWER_ON	= (1 << 2), /* Power up device */
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-	PORT_CMD_SPIN_UP	= (1 << 1), /* Spin up device */
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-	PORT_CMD_START		= (1 << 0), /* Enable port DMA engine */
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+	PORT_CMD_ASP		= BIT(27), /* Aggressive Slumber/Partial */
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+	PORT_CMD_ALPE		= BIT(26), /* Aggressive Link PM enable */
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+	PORT_CMD_ATAPI		= BIT(24), /* Device is ATAPI */
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+	PORT_CMD_FBSCP		= BIT(22), /* FBS Capable Port */
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+	PORT_CMD_ESP		= BIT(21), /* External Sata Port */
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+	PORT_CMD_HPCP		= BIT(18), /* HotPlug Capable Port */
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+	PORT_CMD_PMP		= BIT(17), /* PMP attached */
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+	PORT_CMD_LIST_ON	= BIT(15), /* cmd list DMA engine running */
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+	PORT_CMD_FIS_ON		= BIT(14), /* FIS DMA engine running */
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+	PORT_CMD_FIS_RX		= BIT(4),  /* Enable FIS receive DMA engine */
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+	PORT_CMD_CLO		= BIT(3),  /* Command list override */
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+	PORT_CMD_POWER_ON	= BIT(2),  /* Power up device */
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+	PORT_CMD_SPIN_UP	= BIT(1),  /* Spin up device */
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+	PORT_CMD_START		= BIT(0),  /* Enable port DMA engine */
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-	PORT_CMD_ICC_MASK	= (0xf << 28), /* i/f ICC state mask */
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-	PORT_CMD_ICC_ACTIVE	= (0x1 << 28), /* Put i/f in active state */
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-	PORT_CMD_ICC_PARTIAL	= (0x2 << 28), /* Put i/f in partial state */
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-	PORT_CMD_ICC_SLUMBER	= (0x6 << 28), /* Put i/f in slumber state */
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+	PORT_CMD_ICC_MASK	= (0xfu << 28), /* i/f ICC state mask */
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+	PORT_CMD_ICC_ACTIVE	= (0x1u << 28), /* Put i/f in active state */
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+	PORT_CMD_ICC_PARTIAL	= (0x2u << 28), /* Put i/f in partial state */
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+	PORT_CMD_ICC_SLUMBER	= (0x6u << 28), /* Put i/f in slumber state */
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 	/* PORT_FBS bits */
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 	PORT_FBS_DWE_OFFSET	= 16, /* FBS device with error offset */
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 	PORT_FBS_ADO_OFFSET	= 12, /* FBS active dev optimization offset */
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 	PORT_FBS_DEV_OFFSET	= 8,  /* FBS device to issue offset */
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 	PORT_FBS_DEV_MASK	= (0xf << PORT_FBS_DEV_OFFSET),  /* FBS.DEV */
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-	PORT_FBS_SDE		= (1 << 2), /* FBS single device error */
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-	PORT_FBS_DEC		= (1 << 1), /* FBS device error clear */
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-	PORT_FBS_EN		= (1 << 0), /* Enable FBS */
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+	PORT_FBS_SDE		= BIT(2), /* FBS single device error */
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+	PORT_FBS_DEC		= BIT(1), /* FBS device error clear */
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+	PORT_FBS_EN		= BIT(0), /* Enable FBS */
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 	/* PORT_DEVSLP bits */
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 	PORT_DEVSLP_DM_OFFSET	= 25,             /* DITO multiplier offset */
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@@ -197,52 +198,52 @@
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 	PORT_DEVSLP_DITO_OFFSET	= 15,             /* DITO offset */
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 	PORT_DEVSLP_MDAT_OFFSET	= 10,             /* Minimum assertion time */
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 	PORT_DEVSLP_DETO_OFFSET	= 2,              /* DevSlp exit timeout */
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-	PORT_DEVSLP_DSP		= (1 << 1),       /* DevSlp present */
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-	PORT_DEVSLP_ADSE	= (1 << 0),       /* Aggressive DevSlp enable */
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+	PORT_DEVSLP_DSP		= BIT(1),         /* DevSlp present */
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+	PORT_DEVSLP_ADSE	= BIT(0),         /* Aggressive DevSlp enable */
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 	/* hpriv->flags bits */
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 #define AHCI_HFLAGS(flags)		.private_data	= (void *)(flags)
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-	AHCI_HFLAG_NO_NCQ		= (1 << 0),
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-	AHCI_HFLAG_IGN_IRQ_IF_ERR	= (1 << 1), /* ignore IRQ_IF_ERR */
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-	AHCI_HFLAG_IGN_SERR_INTERNAL	= (1 << 2), /* ignore SERR_INTERNAL */
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-	AHCI_HFLAG_32BIT_ONLY		= (1 << 3), /* force 32bit */
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-	AHCI_HFLAG_MV_PATA		= (1 << 4), /* PATA port */
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-	AHCI_HFLAG_NO_MSI		= (1 << 5), /* no PCI MSI */
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-	AHCI_HFLAG_NO_PMP		= (1 << 6), /* no PMP */
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-	AHCI_HFLAG_SECT255		= (1 << 8), /* max 255 sectors */
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-	AHCI_HFLAG_YES_NCQ		= (1 << 9), /* force NCQ cap on */
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-	AHCI_HFLAG_NO_SUSPEND		= (1 << 10), /* don't suspend */
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-	AHCI_HFLAG_SRST_TOUT_IS_OFFLINE	= (1 << 11), /* treat SRST timeout as
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-							link offline */
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-	AHCI_HFLAG_NO_SNTF		= (1 << 12), /* no sntf */
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-	AHCI_HFLAG_NO_FPDMA_AA		= (1 << 13), /* no FPDMA AA */
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-	AHCI_HFLAG_YES_FBS		= (1 << 14), /* force FBS cap on */
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-	AHCI_HFLAG_DELAY_ENGINE		= (1 << 15), /* do not start engine on
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-						        port start (wait until
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-						        error-handling stage) */
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-	AHCI_HFLAG_NO_DEVSLP		= (1 << 17), /* no device sleep */
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-	AHCI_HFLAG_NO_FBS		= (1 << 18), /* no FBS */
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+	AHCI_HFLAG_NO_NCQ		= BIT(0),
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+	AHCI_HFLAG_IGN_IRQ_IF_ERR	= BIT(1), /* ignore IRQ_IF_ERR */
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+	AHCI_HFLAG_IGN_SERR_INTERNAL	= BIT(2), /* ignore SERR_INTERNAL */
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+	AHCI_HFLAG_32BIT_ONLY		= BIT(3), /* force 32bit */
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+	AHCI_HFLAG_MV_PATA		= BIT(4), /* PATA port */
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+	AHCI_HFLAG_NO_MSI		= BIT(5), /* no PCI MSI */
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+	AHCI_HFLAG_NO_PMP		= BIT(6), /* no PMP */
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+	AHCI_HFLAG_SECT255		= BIT(8), /* max 255 sectors */
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+	AHCI_HFLAG_YES_NCQ		= BIT(9), /* force NCQ cap on */
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+	AHCI_HFLAG_NO_SUSPEND		= BIT(10), /* don't suspend */
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+	AHCI_HFLAG_SRST_TOUT_IS_OFFLINE	= BIT(11), /* treat SRST timeout as
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+						      link offline */
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+	AHCI_HFLAG_NO_SNTF		= BIT(12), /* no sntf */
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+	AHCI_HFLAG_NO_FPDMA_AA		= BIT(13), /* no FPDMA AA */
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+	AHCI_HFLAG_YES_FBS		= BIT(14), /* force FBS cap on */
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+	AHCI_HFLAG_DELAY_ENGINE		= BIT(15), /* do not start engine on
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+						      port start (wait until
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+						      error-handling stage) */
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+	AHCI_HFLAG_NO_DEVSLP		= BIT(17), /* no device sleep */
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+	AHCI_HFLAG_NO_FBS		= BIT(18), /* no FBS */
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 #ifdef CONFIG_PCI_MSI
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-	AHCI_HFLAG_MULTI_MSI		= (1 << 20), /* per-port MSI(-X) */
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+	AHCI_HFLAG_MULTI_MSI		= BIT(20), /* per-port MSI(-X) */
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 #else
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 	/* compile out MSI infrastructure */
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 	AHCI_HFLAG_MULTI_MSI		= 0,
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 #endif
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-	AHCI_HFLAG_WAKE_BEFORE_STOP	= (1 << 22), /* wake before DMA stop */
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-	AHCI_HFLAG_YES_ALPM		= (1 << 23), /* force ALPM cap on */
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-	AHCI_HFLAG_NO_WRITE_TO_RO	= (1 << 24), /* don't write to read
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-							only registers */
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-	AHCI_HFLAG_IS_MOBILE		= (1 << 25), /* mobile chipset, use
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-							SATA_MOBILE_LPM_POLICY
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-							as default lpm_policy */
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-	AHCI_HFLAG_SUSPEND_PHYS		= (1 << 26), /* handle PHYs during
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-							suspend/resume */
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-	AHCI_HFLAG_IGN_NOTSUPP_POWER_ON	= (1 << 27), /* ignore -EOPNOTSUPP
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-							from phy_power_on() */
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-	AHCI_HFLAG_NO_SXS		= (1 << 28), /* SXS not supported */
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+	AHCI_HFLAG_WAKE_BEFORE_STOP	= BIT(22), /* wake before DMA stop */
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+	AHCI_HFLAG_YES_ALPM		= BIT(23), /* force ALPM cap on */
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+	AHCI_HFLAG_NO_WRITE_TO_RO	= BIT(24), /* don't write to read
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+						      only registers */
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+	AHCI_HFLAG_IS_MOBILE            = BIT(25), /* mobile chipset, use
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+						      SATA_MOBILE_LPM_POLICY
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+						      as default lpm_policy */
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+	AHCI_HFLAG_SUSPEND_PHYS		= BIT(26), /* handle PHYs during
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+						      suspend/resume */
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+	AHCI_HFLAG_IGN_NOTSUPP_POWER_ON	= BIT(27), /* ignore -EOPNOTSUPP
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+						      from phy_power_on() */
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+	AHCI_HFLAG_NO_SXS		= BIT(28), /* SXS not supported */
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 	/* ap->flags bits */
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249
 
..
..
@@ -258,22 +259,22 @@
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 	EM_MAX_RETRY			= 5,
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260
 
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 	/* em_ctl bits */
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-	EM_CTL_RST		= (1 << 9), /* Reset */
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-	EM_CTL_TM		= (1 << 8), /* Transmit Message */
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-	EM_CTL_MR		= (1 << 0), /* Message Received */
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-	EM_CTL_ALHD		= (1 << 26), /* Activity LED */
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-	EM_CTL_XMT		= (1 << 25), /* Transmit Only */
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-	EM_CTL_SMB		= (1 << 24), /* Single Message Buffer */
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-	EM_CTL_SGPIO		= (1 << 19), /* SGPIO messages supported */
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-	EM_CTL_SES		= (1 << 18), /* SES-2 messages supported */
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-	EM_CTL_SAFTE		= (1 << 17), /* SAF-TE messages supported */
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-	EM_CTL_LED		= (1 << 16), /* LED messages supported */
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+	EM_CTL_RST		= BIT(9), /* Reset */
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+	EM_CTL_TM		= BIT(8), /* Transmit Message */
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+	EM_CTL_MR		= BIT(0), /* Message Received */
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+	EM_CTL_ALHD		= BIT(26), /* Activity LED */
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+	EM_CTL_XMT		= BIT(25), /* Transmit Only */
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+	EM_CTL_SMB		= BIT(24), /* Single Message Buffer */
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+	EM_CTL_SGPIO		= BIT(19), /* SGPIO messages supported */
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+	EM_CTL_SES		= BIT(18), /* SES-2 messages supported */
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+	EM_CTL_SAFTE		= BIT(17), /* SAF-TE messages supported */
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+	EM_CTL_LED		= BIT(16), /* LED messages supported */
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272
 
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 	/* em message type */
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-	EM_MSG_TYPE_LED		= (1 << 0), /* LED */
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-	EM_MSG_TYPE_SAFTE	= (1 << 1), /* SAF-TE */
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-	EM_MSG_TYPE_SES2	= (1 << 2), /* SES-2 */
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-	EM_MSG_TYPE_SGPIO	= (1 << 3), /* SGPIO */
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+	EM_MSG_TYPE_LED		= BIT(0), /* LED */
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+	EM_MSG_TYPE_SAFTE	= BIT(1), /* SAF-TE */
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+	EM_MSG_TYPE_SES2	= BIT(2), /* SES-2 */
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+	EM_MSG_TYPE_SGPIO	= BIT(3), /* SGPIO */
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 };
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 struct ahci_cmd_hdr {