add new system file

hc

2024-02-20 102a0743326a03cd1a1202ceda21e175b7d3575c

 kernel/drivers/ata/ahci.c
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@@ -1,3 +1,4 @@
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+// SPDX-License-Identifier: GPL-2.0-or-later
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 /*
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  *  ahci.c - AHCI SATA support
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  *
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@@ -7,29 +8,12 @@
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  *
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  *  Copyright 2004-2005 Red Hat, Inc.
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  *
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- *
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- *  This program is free software; you can redistribute it and/or modify
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- *  it under the terms of the GNU General Public License as published by
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- *  the Free Software Foundation; either version 2, or (at your option)
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- *  any later version.
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- *
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- *  This program is distributed in the hope that it will be useful,
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- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
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- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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- *  GNU General Public License for more details.
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- *
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- *  You should have received a copy of the GNU General Public License
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- *  along with this program; see the file COPYING.  If not, write to
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- *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
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- *
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- *
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  * libata documentation is available via 'make {ps|pdf}docs',
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  * as Documentation/driver-api/libata.rst
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  *
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  * AHCI hardware documentation:
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  * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
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  * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
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- *
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  */
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 #include <linux/kernel.h>
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@@ -56,6 +40,7 @@
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 enum {
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 	AHCI_PCI_BAR_STA2X11	= 0,
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 	AHCI_PCI_BAR_CAVIUM	= 0,
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+	AHCI_PCI_BAR_LOONGSON	= 0,
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 	AHCI_PCI_BAR_ENMOTUS	= 2,
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 	AHCI_PCI_BAR_CAVIUM_GEN5	= 4,
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 	AHCI_PCI_BAR_STANDARD	= 5,
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@@ -65,13 +50,15 @@
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 	/* board IDs by feature in alphabetical order */
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 	board_ahci,
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 	board_ahci_ign_iferr,
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-	board_ahci_mobile,
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+	board_ahci_low_power,
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+	board_ahci_no_debounce_delay,
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 	board_ahci_nomsi,
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 	board_ahci_noncq,
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 	board_ahci_nosntf,
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 	board_ahci_yes_fbs,
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 	/* board IDs for specific chipsets in alphabetical order */
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+	board_ahci_al,
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 	board_ahci_avn,
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 	board_ahci_mcp65,
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 	board_ahci_mcp77,
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@@ -97,6 +84,7 @@
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 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
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 static void ahci_remove_one(struct pci_dev *dev);
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 static void ahci_shutdown_one(struct pci_dev *dev);
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+static void ahci_intel_pcs_quirk(struct pci_dev *pdev, struct ahci_host_priv *hpriv);
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 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
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 				 unsigned long deadline);
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 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
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@@ -148,9 +136,16 @@
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 		.udma_mask	= ATA_UDMA6,
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 		.port_ops	= &ahci_ops,
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 	},
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-	[board_ahci_mobile] = {
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+	[board_ahci_low_power] = {
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 		AHCI_HFLAGS	(AHCI_HFLAG_IS_MOBILE),
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 		.flags		= AHCI_FLAG_COMMON,
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+		.pio_mask	= ATA_PIO4,
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+		.udma_mask	= ATA_UDMA6,
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+		.port_ops	= &ahci_ops,
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+	},
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+	[board_ahci_no_debounce_delay] = {
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+		.flags		= AHCI_FLAG_COMMON,
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+		.link_flags	= ATA_LFLAG_NO_DEBOUNCE_DELAY,
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 		.pio_mask	= ATA_PIO4,
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 		.udma_mask	= ATA_UDMA6,
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 		.port_ops	= &ahci_ops,
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@@ -184,6 +179,13 @@
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 		.port_ops	= &ahci_ops,
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 	},
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 	/* by chipsets */
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+	[board_ahci_al] = {
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+		AHCI_HFLAGS	(AHCI_HFLAG_NO_PMP | AHCI_HFLAG_NO_MSI),
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+		.flags		= AHCI_FLAG_COMMON,
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+		.pio_mask	= ATA_PIO4,
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+		.udma_mask	= ATA_UDMA6,
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+		.port_ops	= &ahci_ops,
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+	},
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 	[board_ahci_avn] = {
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 		.flags		= AHCI_FLAG_COMMON,
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 		.pio_mask	= ATA_PIO4,
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@@ -253,6 +255,7 @@
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 static const struct pci_device_id ahci_pci_tbl[] = {
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 	/* Intel */
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+	{ PCI_VDEVICE(INTEL, 0x06d6), board_ahci }, /* Comet Lake PCH-H RAID */
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 	{ PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
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 	{ PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
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 	{ PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
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@@ -273,13 +276,13 @@
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 	{ PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
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 	{ PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
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 	{ PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
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-	{ PCI_VDEVICE(INTEL, 0x2929), board_ahci_mobile }, /* ICH9M */
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-	{ PCI_VDEVICE(INTEL, 0x292a), board_ahci_mobile }, /* ICH9M */
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-	{ PCI_VDEVICE(INTEL, 0x292b), board_ahci_mobile }, /* ICH9M */
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-	{ PCI_VDEVICE(INTEL, 0x292c), board_ahci_mobile }, /* ICH9M */
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-	{ PCI_VDEVICE(INTEL, 0x292f), board_ahci_mobile }, /* ICH9M */
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+	{ PCI_VDEVICE(INTEL, 0x2929), board_ahci_low_power }, /* ICH9M */
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+	{ PCI_VDEVICE(INTEL, 0x292a), board_ahci_low_power }, /* ICH9M */
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+	{ PCI_VDEVICE(INTEL, 0x292b), board_ahci_low_power }, /* ICH9M */
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+	{ PCI_VDEVICE(INTEL, 0x292c), board_ahci_low_power }, /* ICH9M */
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+	{ PCI_VDEVICE(INTEL, 0x292f), board_ahci_low_power }, /* ICH9M */
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 	{ PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
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-	{ PCI_VDEVICE(INTEL, 0x294e), board_ahci_mobile }, /* ICH9M */
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+	{ PCI_VDEVICE(INTEL, 0x294e), board_ahci_low_power }, /* ICH9M */
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 	{ PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
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 	{ PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
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 	{ PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
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@@ -289,9 +292,9 @@
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 	{ PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
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 	{ PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
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 	{ PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
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-	{ PCI_VDEVICE(INTEL, 0x3b29), board_ahci_mobile }, /* PCH M AHCI */
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+	{ PCI_VDEVICE(INTEL, 0x3b29), board_ahci_low_power }, /* PCH M AHCI */
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 	{ PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
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-	{ PCI_VDEVICE(INTEL, 0x3b2c), board_ahci_mobile }, /* PCH M RAID */
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+	{ PCI_VDEVICE(INTEL, 0x3b2c), board_ahci_low_power }, /* PCH M RAID */
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 	{ PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
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 	{ PCI_VDEVICE(INTEL, 0x19b0), board_ahci_pcs7 }, /* DNV AHCI */
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 	{ PCI_VDEVICE(INTEL, 0x19b1), board_ahci_pcs7 }, /* DNV AHCI */
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@@ -314,9 +317,9 @@
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 	{ PCI_VDEVICE(INTEL, 0x19cE), board_ahci_pcs7 }, /* DNV AHCI */
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 	{ PCI_VDEVICE(INTEL, 0x19cF), board_ahci_pcs7 }, /* DNV AHCI */
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 	{ PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
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-	{ PCI_VDEVICE(INTEL, 0x1c03), board_ahci_mobile }, /* CPT M AHCI */
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+	{ PCI_VDEVICE(INTEL, 0x1c03), board_ahci_low_power }, /* CPT M AHCI */
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 	{ PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
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-	{ PCI_VDEVICE(INTEL, 0x1c05), board_ahci_mobile }, /* CPT M RAID */
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+	{ PCI_VDEVICE(INTEL, 0x1c05), board_ahci_low_power }, /* CPT M RAID */
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 	{ PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
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 	{ PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
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 	{ PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
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@@ -325,29 +328,29 @@
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 	{ PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
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 	{ PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
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 	{ PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
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-	{ PCI_VDEVICE(INTEL, 0x1e03), board_ahci_mobile }, /* Panther M AHCI */
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+	{ PCI_VDEVICE(INTEL, 0x1e03), board_ahci_low_power }, /* Panther M AHCI */
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 	{ PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
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 	{ PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
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 	{ PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
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-	{ PCI_VDEVICE(INTEL, 0x1e07), board_ahci_mobile }, /* Panther M RAID */
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+	{ PCI_VDEVICE(INTEL, 0x1e07), board_ahci_low_power }, /* Panther M RAID */
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 	{ PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
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 	{ PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
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-	{ PCI_VDEVICE(INTEL, 0x8c03), board_ahci_mobile }, /* Lynx M AHCI */
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+	{ PCI_VDEVICE(INTEL, 0x8c03), board_ahci_low_power }, /* Lynx M AHCI */
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 	{ PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
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-	{ PCI_VDEVICE(INTEL, 0x8c05), board_ahci_mobile }, /* Lynx M RAID */
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+	{ PCI_VDEVICE(INTEL, 0x8c05), board_ahci_low_power }, /* Lynx M RAID */
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 	{ PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
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-	{ PCI_VDEVICE(INTEL, 0x8c07), board_ahci_mobile }, /* Lynx M RAID */
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+	{ PCI_VDEVICE(INTEL, 0x8c07), board_ahci_low_power }, /* Lynx M RAID */
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 	{ PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
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-	{ PCI_VDEVICE(INTEL, 0x8c0f), board_ahci_mobile }, /* Lynx M RAID */
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-	{ PCI_VDEVICE(INTEL, 0x9c02), board_ahci_mobile }, /* Lynx LP AHCI */
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-	{ PCI_VDEVICE(INTEL, 0x9c03), board_ahci_mobile }, /* Lynx LP AHCI */
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-	{ PCI_VDEVICE(INTEL, 0x9c04), board_ahci_mobile }, /* Lynx LP RAID */
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-	{ PCI_VDEVICE(INTEL, 0x9c05), board_ahci_mobile }, /* Lynx LP RAID */
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-	{ PCI_VDEVICE(INTEL, 0x9c06), board_ahci_mobile }, /* Lynx LP RAID */
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-	{ PCI_VDEVICE(INTEL, 0x9c07), board_ahci_mobile }, /* Lynx LP RAID */
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-	{ PCI_VDEVICE(INTEL, 0x9c0e), board_ahci_mobile }, /* Lynx LP RAID */
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-	{ PCI_VDEVICE(INTEL, 0x9c0f), board_ahci_mobile }, /* Lynx LP RAID */
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-	{ PCI_VDEVICE(INTEL, 0x9dd3), board_ahci_mobile }, /* Cannon Lake PCH-LP AHCI */
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+	{ PCI_VDEVICE(INTEL, 0x8c0f), board_ahci_low_power }, /* Lynx M RAID */
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+	{ PCI_VDEVICE(INTEL, 0x9c02), board_ahci_low_power }, /* Lynx LP AHCI */
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+	{ PCI_VDEVICE(INTEL, 0x9c03), board_ahci_low_power }, /* Lynx LP AHCI */
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+	{ PCI_VDEVICE(INTEL, 0x9c04), board_ahci_low_power }, /* Lynx LP RAID */
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+	{ PCI_VDEVICE(INTEL, 0x9c05), board_ahci_low_power }, /* Lynx LP RAID */
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+	{ PCI_VDEVICE(INTEL, 0x9c06), board_ahci_low_power }, /* Lynx LP RAID */
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+	{ PCI_VDEVICE(INTEL, 0x9c07), board_ahci_low_power }, /* Lynx LP RAID */
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+	{ PCI_VDEVICE(INTEL, 0x9c0e), board_ahci_low_power }, /* Lynx LP RAID */
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+	{ PCI_VDEVICE(INTEL, 0x9c0f), board_ahci_low_power }, /* Lynx LP RAID */
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+	{ PCI_VDEVICE(INTEL, 0x9dd3), board_ahci_low_power }, /* Cannon Lake PCH-LP AHCI */
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 	{ PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */
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 	{ PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */
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 	{ PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
..
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@@ -366,6 +369,10 @@
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 	{ PCI_VDEVICE(INTEL, 0x1f3f), board_ahci_avn }, /* Avoton RAID */
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 	{ PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg RAID */
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 	{ PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Wellsburg RAID */
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+	{ PCI_VDEVICE(INTEL, 0x43d4), board_ahci }, /* Rocket Lake PCH-H RAID */
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+	{ PCI_VDEVICE(INTEL, 0x43d5), board_ahci }, /* Rocket Lake PCH-H RAID */
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+	{ PCI_VDEVICE(INTEL, 0x43d6), board_ahci }, /* Rocket Lake PCH-H RAID */
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+	{ PCI_VDEVICE(INTEL, 0x43d7), board_ahci }, /* Rocket Lake PCH-H RAID */
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 	{ PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */
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 	{ PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */
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 	{ PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */
..
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@@ -375,26 +382,26 @@
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 	{ PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */
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 	{ PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */
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 	{ PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */
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-	{ PCI_VDEVICE(INTEL, 0x9c83), board_ahci_mobile }, /* Wildcat LP AHCI */
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-	{ PCI_VDEVICE(INTEL, 0x9c85), board_ahci_mobile }, /* Wildcat LP RAID */
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-	{ PCI_VDEVICE(INTEL, 0x9c87), board_ahci_mobile }, /* Wildcat LP RAID */
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-	{ PCI_VDEVICE(INTEL, 0x9c8f), board_ahci_mobile }, /* Wildcat LP RAID */
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+	{ PCI_VDEVICE(INTEL, 0x9c83), board_ahci_low_power }, /* Wildcat LP AHCI */
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+	{ PCI_VDEVICE(INTEL, 0x9c85), board_ahci_low_power }, /* Wildcat LP RAID */
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+	{ PCI_VDEVICE(INTEL, 0x9c87), board_ahci_low_power }, /* Wildcat LP RAID */
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+	{ PCI_VDEVICE(INTEL, 0x9c8f), board_ahci_low_power }, /* Wildcat LP RAID */
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 	{ PCI_VDEVICE(INTEL, 0x8c82), board_ahci }, /* 9 Series AHCI */
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-	{ PCI_VDEVICE(INTEL, 0x8c83), board_ahci_mobile }, /* 9 Series M AHCI */
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+	{ PCI_VDEVICE(INTEL, 0x8c83), board_ahci_low_power }, /* 9 Series M AHCI */
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 	{ PCI_VDEVICE(INTEL, 0x8c84), board_ahci }, /* 9 Series RAID */
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-	{ PCI_VDEVICE(INTEL, 0x8c85), board_ahci_mobile }, /* 9 Series M RAID */
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+	{ PCI_VDEVICE(INTEL, 0x8c85), board_ahci_low_power }, /* 9 Series M RAID */
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 	{ PCI_VDEVICE(INTEL, 0x8c86), board_ahci }, /* 9 Series RAID */
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-	{ PCI_VDEVICE(INTEL, 0x8c87), board_ahci_mobile }, /* 9 Series M RAID */
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+	{ PCI_VDEVICE(INTEL, 0x8c87), board_ahci_low_power }, /* 9 Series M RAID */
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 	{ PCI_VDEVICE(INTEL, 0x8c8e), board_ahci }, /* 9 Series RAID */
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-	{ PCI_VDEVICE(INTEL, 0x8c8f), board_ahci_mobile }, /* 9 Series M RAID */
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-	{ PCI_VDEVICE(INTEL, 0x9d03), board_ahci_mobile }, /* Sunrise LP AHCI */
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-	{ PCI_VDEVICE(INTEL, 0x9d05), board_ahci_mobile }, /* Sunrise LP RAID */
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-	{ PCI_VDEVICE(INTEL, 0x9d07), board_ahci_mobile }, /* Sunrise LP RAID */
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+	{ PCI_VDEVICE(INTEL, 0x8c8f), board_ahci_low_power }, /* 9 Series M RAID */
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+	{ PCI_VDEVICE(INTEL, 0x9d03), board_ahci_low_power }, /* Sunrise LP AHCI */
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+	{ PCI_VDEVICE(INTEL, 0x9d05), board_ahci_low_power }, /* Sunrise LP RAID */
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+	{ PCI_VDEVICE(INTEL, 0x9d07), board_ahci_low_power }, /* Sunrise LP RAID */
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 	{ PCI_VDEVICE(INTEL, 0xa102), board_ahci }, /* Sunrise Point-H AHCI */
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-	{ PCI_VDEVICE(INTEL, 0xa103), board_ahci_mobile }, /* Sunrise M AHCI */
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+	{ PCI_VDEVICE(INTEL, 0xa103), board_ahci_low_power }, /* Sunrise M AHCI */
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 	{ PCI_VDEVICE(INTEL, 0xa105), board_ahci }, /* Sunrise Point-H RAID */
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 	{ PCI_VDEVICE(INTEL, 0xa106), board_ahci }, /* Sunrise Point-H RAID */
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-	{ PCI_VDEVICE(INTEL, 0xa107), board_ahci_mobile }, /* Sunrise M RAID */
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+	{ PCI_VDEVICE(INTEL, 0xa107), board_ahci_low_power }, /* Sunrise M RAID */
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 	{ PCI_VDEVICE(INTEL, 0xa10f), board_ahci }, /* Sunrise Point-H RAID */
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 	{ PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* Lewisburg RAID*/
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 	{ PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Lewisburg AHCI*/
..
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@@ -410,11 +417,16 @@
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 	{ PCI_VDEVICE(INTEL, 0xa256), board_ahci }, /* Lewisburg RAID*/
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 	{ PCI_VDEVICE(INTEL, 0xa356), board_ahci }, /* Cannon Lake PCH-H RAID */
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 	{ PCI_VDEVICE(INTEL, 0x06d7), board_ahci }, /* Comet Lake-H RAID */
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-	{ PCI_VDEVICE(INTEL, 0x0f22), board_ahci_mobile }, /* Bay Trail AHCI */
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-	{ PCI_VDEVICE(INTEL, 0x0f23), board_ahci_mobile }, /* Bay Trail AHCI */
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-	{ PCI_VDEVICE(INTEL, 0x22a3), board_ahci_mobile }, /* Cherry Tr. AHCI */
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-	{ PCI_VDEVICE(INTEL, 0x5ae3), board_ahci_mobile }, /* ApolloLake AHCI */
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-	{ PCI_VDEVICE(INTEL, 0x34d3), board_ahci_mobile }, /* Ice Lake LP AHCI */
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+	{ PCI_VDEVICE(INTEL, 0xa386), board_ahci }, /* Comet Lake PCH-V RAID */
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+	{ PCI_VDEVICE(INTEL, 0x0f22), board_ahci_low_power }, /* Bay Trail AHCI */
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+	{ PCI_VDEVICE(INTEL, 0x0f23), board_ahci_low_power }, /* Bay Trail AHCI */
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+	{ PCI_VDEVICE(INTEL, 0x22a3), board_ahci_low_power }, /* Cherry Tr. AHCI */
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+	{ PCI_VDEVICE(INTEL, 0x5ae3), board_ahci_low_power }, /* ApolloLake AHCI */
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+	{ PCI_VDEVICE(INTEL, 0x34d3), board_ahci_low_power }, /* Ice Lake LP AHCI */
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+	{ PCI_VDEVICE(INTEL, 0x02d3), board_ahci_low_power }, /* Comet Lake PCH-U AHCI */
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+	{ PCI_VDEVICE(INTEL, 0x02d7), board_ahci_low_power }, /* Comet Lake PCH RAID */
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+	/* Elkhart Lake IDs 0x4b60 & 0x4b62 https://sata-io.org/product/8803 not tested yet */
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+	{ PCI_VDEVICE(INTEL, 0x4b63), board_ahci_low_power }, /* Elkhart Lake AHCI */
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 	/* JMicron 360/1/3/5/6, match class to avoid IDE function */
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 	{ PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
..
..
@@ -433,10 +445,16 @@
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 	{ PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
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 	{ PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
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+	/* Amazon's Annapurna Labs support */
449
+	{ PCI_DEVICE(PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031),
450
+		.class = PCI_CLASS_STORAGE_SATA_AHCI,
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+		.class_mask = 0xffffff,
452
+		board_ahci_al },
436
453
 	/* AMD */
437
454
 	{ PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
455
+	{ PCI_VDEVICE(AMD, 0x7801), board_ahci_no_debounce_delay }, /* AMD Hudson-2 (AHCI mode) */
438
456
 	{ PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */
439
-	{ PCI_VDEVICE(AMD, 0x7901), board_ahci_mobile }, /* AMD Green Sardine */
457
+	{ PCI_VDEVICE(AMD, 0x7901), board_ahci_low_power }, /* AMD Green Sardine */
440
458
 	/* AMD is using RAID class only for ahci controllers */
441
459
 	{ PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
442
460
 	  PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
..
..
@@ -594,6 +612,9 @@
594
612
 	/* Enmotus */
595
613
 	{ PCI_DEVICE(0x1c44, 0x8000), board_ahci },
596
614
 
615
+	/* Loongson */
616
+	{ PCI_VDEVICE(LOONGSON, 0x7a08), board_ahci },
617
+
597
618
 	/* Generic, PCI class code for AHCI */
598
619
 	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
599
620
 	  PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
..
..
@@ -655,6 +676,25 @@
655
676
 	ahci_save_initial_config(&pdev->dev, hpriv);
656
677
 }
657
678
 
679
+static int ahci_pci_reset_controller(struct ata_host *host)
680
+{
681
+	struct pci_dev *pdev = to_pci_dev(host->dev);
682
+	struct ahci_host_priv *hpriv = host->private_data;
683
+	int rc;
684
+
685
+	rc = ahci_reset_controller(host);
686
+	if (rc)
687
+		return rc;
688
+
689
+	/*
690
+	 * If platform firmware failed to enable ports, try to enable
691
+	 * them here.
692
+	 */
693
+	ahci_intel_pcs_quirk(pdev, hpriv);
694
+
695
+	return 0;
696
+}
697
+
658
698
 static void ahci_pci_init_controller(struct ata_host *host)
659
699
 {
660
700
 	struct ahci_host_priv *hpriv = host->private_data;
..
..
@@ -674,7 +714,7 @@
674
714
 
675
715
 		/* clear port IRQ */
676
716
 		tmp = readl(port_mmio + PORT_IRQ_STAT);
677
-		VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
717
+		dev_dbg(&pdev->dev, "PORT_IRQ_STAT 0x%x\n", tmp);
678
718
 		if (tmp)
679
719
 			writel(tmp, port_mmio + PORT_IRQ_STAT);
680
720
 	}
..
..
@@ -803,8 +843,7 @@
803
843
 				(sstatus & 0xf) != 1)
804
844
 			break;
805
845
 
806
-		ata_link_printk(link, KERN_INFO, "avn bounce port%d\n",
807
-				port);
846
+		ata_link_info(link,  "avn bounce port%d\n", port);
808
847
 
809
848
 		pci_read_config_word(pdev, 0x92, &val);
810
849
 		val &= ~(1 << port);
..
..
@@ -857,7 +896,7 @@
857
896
 	struct ata_host *host = pci_get_drvdata(pdev);
858
897
 	int rc;
859
898
 
860
-	rc = ahci_reset_controller(host);
899
+	rc = ahci_pci_reset_controller(host);
861
900
 	if (rc)
862
901
 		return rc;
863
902
 	ahci_pci_init_controller(host);
..
..
@@ -892,7 +931,7 @@
892
931
 		ahci_mcp89_apple_enable(pdev);
893
932
 
894
933
 	if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
895
-		rc = ahci_reset_controller(host);
934
+		rc = ahci_pci_reset_controller(host);
896
935
 		if (rc)
897
936
 			return rc;
898
937
 
..
..
@@ -909,40 +948,23 @@
909
948
 
910
949
 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
911
950
 {
951
+	const int dma_bits = using_dac ? 64 : 32;
912
952
 	int rc;
913
953
 
914
954
 	/*
915
955
 	 * If the device fixup already set the dma_mask to some non-standard
916
956
 	 * value, don't extend it here. This happens on STA2X11, for example.
957
+	 *
958
+	 * XXX: manipulating the DMA mask from platform code is completely
959
+	 * bogus, platform code should use dev->bus_dma_limit instead..
917
960
 	 */
918
961
 	if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
919
962
 		return 0;
920
963
 
921
-	if (using_dac &&
922
-	    !dma_set_mask(&pdev->dev, DMA_BIT_MASK(64))) {
923
-		rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
924
-		if (rc) {
925
-			rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
926
-			if (rc) {
927
-				dev_err(&pdev->dev,
928
-					"64-bit DMA enable failed\n");
929
-				return rc;
930
-			}
931
-		}
932
-	} else {
933
-		rc = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
934
-		if (rc) {
935
-			dev_err(&pdev->dev, "32-bit DMA enable failed\n");
936
-			return rc;
937
-		}
938
-		rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
939
-		if (rc) {
940
-			dev_err(&pdev->dev,
941
-				"32-bit consistent DMA enable failed\n");
942
-			return rc;
943
-		}
944
-	}
945
-	return 0;
964
+	rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(dma_bits));
965
+	if (rc)
966
+		dev_err(&pdev->dev, "DMA enable failed\n");
967
+	return rc;
946
968
 }
947
969
 
948
970
 static void ahci_pci_print_info(struct ata_host *host)
..
..
@@ -1484,7 +1506,6 @@
1484
1506
 	u32 irq_stat, irq_masked;
1485
1507
 	unsigned int handled = 1;
1486
1508
 
1487
-	VPRINTK("ENTER\n");
1488
1509
 	hpriv = host->private_data;
1489
1510
 	mmio = hpriv->mmio;
1490
1511
 	irq_stat = readl(mmio + HOST_IRQ_STAT);
..
..
@@ -1501,7 +1522,6 @@
1501
1522
 		irq_stat = readl(mmio + HOST_IRQ_STAT);
1502
1523
 		spin_unlock(&host->lock);
1503
1524
 	} while (irq_stat);
1504
-	VPRINTK("EXIT\n");
1505
1525
 
1506
1526
 	return IRQ_RETVAL(handled);
1507
1527
 }
..
..
@@ -1510,7 +1530,7 @@
1510
1530
 static void ahci_remap_check(struct pci_dev *pdev, int bar,
1511
1531
 		struct ahci_host_priv *hpriv)
1512
1532
 {
1513
-	int i, count = 0;
1533
+	int i;
1514
1534
 	u32 cap;
1515
1535
 
1516
1536
 	/*
..
..
@@ -1531,13 +1551,14 @@
1531
1551
 			continue;
1532
1552
 
1533
1553
 		/* We've found a remapped device */
1534
-		count++;
1554
+		hpriv->remapped_nvme++;
1535
1555
 	}
1536
1556
 
1537
-	if (!count)
1557
+	if (!hpriv->remapped_nvme)
1538
1558
 		return;
1539
1559
 
1540
-	dev_warn(&pdev->dev, "Found %d remapped NVMe devices.\n", count);
1560
+	dev_warn(&pdev->dev, "Found %u remapped NVMe devices.\n",
1561
+		 hpriv->remapped_nvme);
1541
1562
 	dev_warn(&pdev->dev,
1542
1563
 		 "Switch your BIOS from RAID to AHCI mode to use them.\n");
1543
1564
 
..
..
@@ -1657,6 +1678,18 @@
1657
1678
 	}
1658
1679
 }
1659
1680
 
1681
+static ssize_t remapped_nvme_show(struct device *dev,
1682
+				  struct device_attribute *attr,
1683
+				  char *buf)
1684
+{
1685
+	struct ata_host *host = dev_get_drvdata(dev);
1686
+	struct ahci_host_priv *hpriv = host->private_data;
1687
+
1688
+	return sprintf(buf, "%u\n", hpriv->remapped_nvme);
1689
+}
1690
+
1691
+static DEVICE_ATTR_RO(remapped_nvme);
1692
+
1660
1693
 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1661
1694
 {
1662
1695
 	unsigned int board_id = ent->driver_data;
..
..
@@ -1702,6 +1735,9 @@
1702
1735
 			ahci_pci_bar = AHCI_PCI_BAR_CAVIUM;
1703
1736
 		if (pdev->device == 0xa084)
1704
1737
 			ahci_pci_bar = AHCI_PCI_BAR_CAVIUM_GEN5;
1738
+	} else if (pdev->vendor == PCI_VENDOR_ID_LOONGSON) {
1739
+		if (pdev->device == 0x7a08)
1740
+			ahci_pci_bar = AHCI_PCI_BAR_LOONGSON;
1705
1741
 	}
1706
1742
 
1707
1743
 	/* acquire resources */
..
..
@@ -1757,23 +1793,26 @@
1757
1793
 	/* detect remapped nvme devices */
1758
1794
 	ahci_remap_check(pdev, ahci_pci_bar, hpriv);
1759
1795
 
1796
+	sysfs_add_file_to_group(&pdev->dev.kobj,
1797
+				&dev_attr_remapped_nvme.attr,
1798
+				NULL);
1799
+
1760
1800
 	/* must set flag prior to save config in order to take effect */
1761
1801
 	if (ahci_broken_devslp(pdev))
1762
1802
 		hpriv->flags |= AHCI_HFLAG_NO_DEVSLP;
1763
1803
 
1764
1804
 #ifdef CONFIG_ARM64
1805
+	if (pdev->vendor == PCI_VENDOR_ID_HUAWEI &&
1806
+	    pdev->device == 0xa235 &&
1807
+	    pdev->revision < 0x30)
1808
+		hpriv->flags |= AHCI_HFLAG_NO_SXS;
1809
+
1765
1810
 	if (pdev->vendor == 0x177d && pdev->device == 0xa01c)
1766
1811
 		hpriv->irq_handler = ahci_thunderx_irq_handler;
1767
1812
 #endif
1768
1813
 
1769
1814
 	/* save initial config */
1770
1815
 	ahci_pci_save_initial_config(pdev, hpriv);
1771
-
1772
-	/*
1773
-	 * If platform firmware failed to enable ports, try to enable
1774
-	 * them here.
1775
-	 */
1776
-	ahci_intel_pcs_quirk(pdev, hpriv);
1777
1816
 
1778
1817
 	/* prepare host */
1779
1818
 	if (hpriv->cap & HOST_CAP_NCQ) {
..
..
@@ -1852,6 +1891,15 @@
1852
1891
 	else
1853
1892
 		dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n");
1854
1893
 
1894
+	if (!(hpriv->cap & HOST_CAP_PART))
1895
+		host->flags |= ATA_HOST_NO_PART;
1896
+
1897
+	if (!(hpriv->cap & HOST_CAP_SSC))
1898
+		host->flags |= ATA_HOST_NO_SSC;
1899
+
1900
+	if (!(hpriv->cap2 & HOST_CAP2_SDS))
1901
+		host->flags |= ATA_HOST_NO_DEVSLP;
1902
+
1855
1903
 	if (pi.flags & ATA_FLAG_EM)
1856
1904
 		ahci_reset_em(host);
1857
1905
 
..
..
@@ -1884,7 +1932,7 @@
1884
1932
 	if (rc)
1885
1933
 		return rc;
1886
1934
 
1887
-	rc = ahci_reset_controller(host);
1935
+	rc = ahci_pci_reset_controller(host);
1888
1936
 	if (rc)
1889
1937
 		return rc;
1890
1938
 
..
..
@@ -1908,6 +1956,9 @@
1908
1956
 
1909
1957
 static void ahci_remove_one(struct pci_dev *pdev)
1910
1958
 {
1959
+	sysfs_remove_file_from_group(&pdev->dev.kobj,
1960
+				     &dev_attr_remapped_nvme.attr,
1961
+				     NULL);
1911
1962
 	pm_runtime_get_noresume(&pdev->dev);
1912
1963
 	ata_pci_remove_one(pdev);
1913
1964
 }