hc
2024-02-20 102a0743326a03cd1a1202ceda21e175b7d3575c
kernel/arch/xtensa/kernel/perf_event.c
....@@ -13,17 +13,26 @@
1313 #include <linux/perf_event.h>
1414 #include <linux/platform_device.h>
1515
16
+#include <asm/core.h>
1617 #include <asm/processor.h>
1718 #include <asm/stacktrace.h>
1819
20
+#define XTENSA_HWVERSION_RG_2015_0 260000
21
+
22
+#if XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RG_2015_0
23
+#define XTENSA_PMU_ERI_BASE 0x00101000
24
+#else
25
+#define XTENSA_PMU_ERI_BASE 0x00001000
26
+#endif
27
+
1928 /* Global control/status for all perf counters */
20
-#define XTENSA_PMU_PMG 0x1000
29
+#define XTENSA_PMU_PMG XTENSA_PMU_ERI_BASE
2130 /* Perf counter values */
22
-#define XTENSA_PMU_PM(i) (0x1080 + (i) * 4)
31
+#define XTENSA_PMU_PM(i) (XTENSA_PMU_ERI_BASE + 0x80 + (i) * 4)
2332 /* Perf counter control registers */
24
-#define XTENSA_PMU_PMCTRL(i) (0x1100 + (i) * 4)
33
+#define XTENSA_PMU_PMCTRL(i) (XTENSA_PMU_ERI_BASE + 0x100 + (i) * 4)
2534 /* Perf counter status registers */
26
-#define XTENSA_PMU_PMSTAT(i) (0x1180 + (i) * 4)
35
+#define XTENSA_PMU_PMSTAT(i) (XTENSA_PMU_ERI_BASE + 0x180 + (i) * 4)
2736
2837 #define XTENSA_PMU_PMG_PMEN 0x1
2938