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2024-02-20 102a0743326a03cd1a1202ceda21e175b7d3575c

 kernel/arch/xtensa/include/asm/initialize_mmu.h
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@@ -6,7 +6,7 @@
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  *      For the new V3 MMU we remap the TLB from virtual == physical
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  *      to the standard Linux mapping used in earlier MMU's.
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  *
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- *      The the MMU we also support a new configuration register that
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+ *      For the MMU we also support a new configuration register that
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  *      specifies how the S32C1I instruction operates with the cache
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  *      controller.
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  *
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@@ -23,7 +23,8 @@
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 #ifndef _XTENSA_INITIALIZE_MMU_H
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 #define _XTENSA_INITIALIZE_MMU_H
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-#include <asm/pgtable.h>
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+#include <linux/init.h>
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+#include <linux/pgtable.h>
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 #include <asm/vectors.h>
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 #if XCHAL_HAVE_PTP_MMU
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@@ -31,10 +32,6 @@
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 #define CA_WRITEBACK	(_PAGE_CA_WB     | _PAGE_HW_WRITE | _PAGE_HW_EXEC)
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 #else
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 #define CA_WRITEBACK	(0x4)
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-#endif
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-
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-#ifndef XCHAL_SPANNING_WAY
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-#define XCHAL_SPANNING_WAY 0
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 #endif
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 #ifdef __ASSEMBLY__
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@@ -46,7 +43,7 @@
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 #if XCHAL_HAVE_S32C1I && (XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RC_2009_0)
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 /*
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  * We Have Atomic Operation Control (ATOMCTL) Register; Initialize it.
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- * For details see Documentation/xtensa/atomctl.txt
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+ * For details see Documentation/xtensa/atomctl.rst
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  */
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 #if XCHAL_DCACHE_IS_COHERENT
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 	movi	a3, 0x25	/* For SMP/MX -- internal for writeback,
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@@ -181,11 +178,42 @@
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 	.macro	initialize_cacheattr
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-#if !defined(CONFIG_MMU) && XCHAL_HAVE_TLBS
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+#if !defined(CONFIG_MMU) && (XCHAL_HAVE_TLBS || XCHAL_HAVE_MPU)
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 #if CONFIG_MEMMAP_CACHEATTR == 0x22222222 && XCHAL_HAVE_PTP_MMU
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 #error Default MEMMAP_CACHEATTR of 0x22222222 does not work with full MMU.
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 #endif
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+#if XCHAL_HAVE_MPU
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+	__REFCONST
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+	.align	4
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+.Lattribute_table:
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+	.long 0x000000, 0x1fff00, 0x1ddf00, 0x1eef00
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+	.long 0x006600, 0x000000, 0x000000, 0x000000
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+	.long 0x000000, 0x000000, 0x000000, 0x000000
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+	.long 0x000000, 0x000000, 0x000000, 0x000000
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+	.previous
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+
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+	movi	a3, .Lattribute_table
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+	movi	a4, CONFIG_MEMMAP_CACHEATTR
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+	movi	a5, 1
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+	movi	a6, XCHAL_MPU_ENTRIES
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+	movi	a10, 0x20000000
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+	movi	a11, -1
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+1:
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+	sub	a5, a5, a10
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+	extui	a8, a4, 28, 4
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+	beq	a8, a11, 2f
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+	addi	a6, a6, -1
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+	mov	a11, a8
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+2:
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+	addx4	a9, a8, a3
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+	l32i	a9, a9, 0
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+	or	a9, a9, a6
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+	wptlb	a9, a5
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+	slli	a4, a4, 4
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+	bgeu	a5, a10, 1b
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+
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+#else
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 	movi	a5, XCHAL_SPANNING_WAY
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 	movi	a6, ~_PAGE_ATTRIB_MASK
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 	movi	a4, CONFIG_MEMMAP_CACHEATTR
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@@ -208,6 +236,7 @@
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 	isync
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 #endif
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+#endif
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 	.endm
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