.. | .. |
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26 | 26 | #include <asm/fpu/api.h> |
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27 | 27 | #include <asm/asm.h> |
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28 | 28 | |
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| 29 | +/* |
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| 30 | + * Use KFPU_387. MMX instructions are not affected by MXCSR, |
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| 31 | + * but both AMD and Intel documentation states that even integer MMX |
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| 32 | + * operations will result in #MF if an exception is pending in FCW. |
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| 33 | + * |
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| 34 | + * EMMS is not needed afterwards because, after calling kernel_fpu_end(), |
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| 35 | + * any subsequent user of the 387 stack will reinitialize it using |
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| 36 | + * KFPU_387. |
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| 37 | + */ |
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| 38 | + |
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29 | 39 | void *_mmx_memcpy(void *to, const void *from, size_t len) |
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30 | 40 | { |
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31 | 41 | void *p; |
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.. | .. |
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37 | 47 | p = to; |
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38 | 48 | i = len >> 6; /* len/64 */ |
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39 | 49 | |
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40 | | - kernel_fpu_begin(); |
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| 50 | + kernel_fpu_begin_mask(KFPU_387); |
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41 | 51 | |
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42 | 52 | __asm__ __volatile__ ( |
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43 | 53 | "1: prefetch (%0)\n" /* This set is 28 bytes */ |
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.. | .. |
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127 | 137 | { |
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128 | 138 | int i; |
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129 | 139 | |
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130 | | - kernel_fpu_begin(); |
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| 140 | + kernel_fpu_begin_mask(KFPU_387); |
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131 | 141 | |
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132 | 142 | __asm__ __volatile__ ( |
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133 | 143 | " pxor %%mm0, %%mm0\n" : : |
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.. | .. |
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160 | 170 | { |
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161 | 171 | int i; |
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162 | 172 | |
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163 | | - kernel_fpu_begin(); |
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| 173 | + kernel_fpu_begin_mask(KFPU_387); |
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164 | 174 | |
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165 | 175 | /* |
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166 | 176 | * maybe the prefetch stuff can go before the expensive fnsave... |
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.. | .. |
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247 | 257 | { |
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248 | 258 | int i; |
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249 | 259 | |
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250 | | - kernel_fpu_begin(); |
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| 260 | + kernel_fpu_begin_mask(KFPU_387); |
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251 | 261 | |
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252 | 262 | __asm__ __volatile__ ( |
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253 | 263 | " pxor %%mm0, %%mm0\n" : : |
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.. | .. |
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282 | 292 | { |
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283 | 293 | int i; |
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284 | 294 | |
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285 | | - kernel_fpu_begin(); |
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| 295 | + kernel_fpu_begin_mask(KFPU_387); |
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286 | 296 | |
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287 | 297 | __asm__ __volatile__ ( |
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288 | 298 | "1: prefetch (%0)\n" |
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