add new system file

hc

2024-02-20 102a0743326a03cd1a1202ceda21e175b7d3575c

 kernel/arch/x86/kernel/quirks.c
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@@ -7,6 +7,8 @@
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 #include <linux/irq.h>
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 #include <asm/hpet.h>
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+#include <asm/setup.h>
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+#include <asm/mce.h>
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 #if defined(CONFIG_X86_IO_APIC) && defined(CONFIG_SMP) && defined(CONFIG_PCI)
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@@ -89,14 +91,12 @@
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 		BUG();
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 	else
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 		printk(KERN_DEBUG "Force enabled HPET at resume\n");
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-
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-	return;
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 }
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 static void ich_force_enable_hpet(struct pci_dev *dev)
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 {
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 	u32 val;
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-	u32 uninitialized_var(rcba);
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+	u32 rcba;
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 	int err = 0;
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 	if (hpet_address || force_hpet_address)
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@@ -111,7 +111,7 @@
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 	}
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 	/* use bits 31:14, 16 kB aligned */
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-	rcba_base = ioremap_nocache(rcba, 0x4000);
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+	rcba_base = ioremap(rcba, 0x4000);
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 	if (rcba_base == NULL) {
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 		dev_printk(KERN_DEBUG, &dev->dev, "ioremap failed; "
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 			"cannot force enable HPET\n");
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@@ -186,7 +186,7 @@
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 static void old_ich_force_hpet_resume(void)
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 {
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 	u32 val;
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-	u32 uninitialized_var(gen_cntl);
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+	u32 gen_cntl;
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 	if (!force_hpet_address || !cached_dev)
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 		return;
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@@ -208,7 +208,7 @@
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 static void old_ich_force_enable_hpet(struct pci_dev *dev)
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 {
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 	u32 val;
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-	u32 uninitialized_var(gen_cntl);
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+	u32 gen_cntl;
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 	if (hpet_address || force_hpet_address)
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 		return;
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@@ -299,7 +299,7 @@
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 static void vt8237_force_enable_hpet(struct pci_dev *dev)
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 {
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-	u32 uninitialized_var(val);
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+	u32 val;
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 	if (hpet_address || force_hpet_address)
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 		return;
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@@ -430,7 +430,7 @@
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 static void nvidia_force_enable_hpet(struct pci_dev *dev)
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 {
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-	u32 uninitialized_var(val);
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+	u32 val;
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 	if (hpet_address || force_hpet_address)
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 		return;
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@@ -447,7 +447,6 @@
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 	dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at 0x%lx\n",
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 		force_hpet_address);
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 	cached_dev = dev;
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-	return;
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 }
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 /* ISA Bridges */
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@@ -512,7 +511,6 @@
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 	force_hpet_resume_type = NONE_FORCE_HPET_RESUME;
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 	dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at "
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 		"0x%lx\n", force_hpet_address);
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-	return;
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 }
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 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E6XX_CU,
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 			 e6xx_force_enable_hpet);
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@@ -627,10 +625,6 @@
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 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_NB_F3,
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 			amd_disable_seq_and_redirect_scrub);
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-#if defined(CONFIG_X86_64) && defined(CONFIG_X86_MCE)
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-#include <linux/jump_label.h>
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-#include <asm/string_64.h>
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-
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 /* Ivy Bridge, Haswell, Broadwell */
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 static void quirk_intel_brickland_xeon_ras_cap(struct pci_dev *pdev)
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 {
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@@ -639,7 +633,7 @@
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 	pci_read_config_dword(pdev, 0x84, &capid0);
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 	if (capid0 & 0x10)
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-		static_branch_inc(&mcsafe_key);
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+		enable_copy_mc_fragile();
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 }
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 /* Skylake */
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@@ -656,14 +650,13 @@
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 	 * enabled, so memory machine check recovery is also enabled.
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 	 */
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 	if ((capid0 & 0xc0) == 0xc0 || (capid5 & 0x1e0))
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-		static_branch_inc(&mcsafe_key);
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+		enable_copy_mc_fragile();
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 }
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 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x0ec3, quirk_intel_brickland_xeon_ras_cap);
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 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x2fc0, quirk_intel_brickland_xeon_ras_cap);
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 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x6fc0, quirk_intel_brickland_xeon_ras_cap);
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 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x2083, quirk_intel_purley_xeon_ras_cap);
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-#endif
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 #endif
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 bool x86_apple_machine;