add new system file

hc

2024-02-20 102a0743326a03cd1a1202ceda21e175b7d3575c

 kernel/arch/x86/kernel/irqinit.c
..
..
@@ -16,12 +16,14 @@
16
16
 #include <linux/acpi.h>
17
17
 #include <linux/io.h>
18
18
 #include <linux/delay.h>
19
+#include <linux/pgtable.h>
19
20
 
20
21
 #include <linux/atomic.h>
21
22
 #include <asm/timer.h>
22
23
 #include <asm/hw_irq.h>
23
-#include <asm/pgtable.h>
24
24
 #include <asm/desc.h>
25
+#include <asm/io_apic.h>
26
+#include <asm/acpi.h>
25
27
 #include <asm/apic.h>
26
28
 #include <asm/setup.h>
27
29
 #include <asm/i8259.h>
..
..
@@ -44,15 +46,6 @@
44
46
  * (these are usually mapped into the 0x30-0xff vector range)
45
47
  */
46
48
 
47
-/*
48
- * IRQ2 is cascade interrupt to second interrupt controller
49
- */
50
-static struct irqaction irq2 = {
51
-	.handler = no_action,
52
-	.name = "cascade",
53
-	.flags = IRQF_NO_THREAD,
54
-};
55
-
56
49
 DEFINE_PER_CPU(vector_irq_t, vector_irq) = {
57
50
 	[0 ... NR_VECTORS - 1] = VECTOR_UNUSED,
58
51
 };
..
..
@@ -72,8 +65,10 @@
72
65
 
73
66
 	legacy_pic->init(0);
74
67
 
75
-	for (i = 0; i < nr_legacy_irqs(); i++)
68
+	for (i = 0; i < nr_legacy_irqs(); i++) {
76
69
 		irq_set_chip_and_handler(i, chip, handle_level_irq);
70
+		irq_set_status_flags(i, IRQ_LEVEL);
71
+	}
77
72
 }
78
73
 
79
74
 void __init init_IRQ(void)
..
..
@@ -84,12 +79,14 @@
84
79
 	 * On cpu 0, Assign ISA_IRQ_VECTOR(irq) to IRQ 0..15.
85
80
 	 * If these IRQ's are handled by legacy interrupt-controllers like PIC,
86
81
 	 * then this configuration will likely be static after the boot. If
87
-	 * these IRQ's are handled by more mordern controllers like IO-APIC,
82
+	 * these IRQs are handled by more modern controllers like IO-APIC,
88
83
 	 * then this vector space can be freed and re-used dynamically as the
89
84
 	 * irq's migrate etc.
90
85
 	 */
91
86
 	for (i = 0; i < nr_legacy_irqs(); i++)
92
87
 		per_cpu(vector_irq, 0)[ISA_IRQ_VECTOR(i)] = irq_to_desc(i);
88
+
89
+	BUG_ON(irq_init_percpu_irqstack(smp_processor_id()));
93
90
 
94
91
 	x86_init.irqs.intr_init();
95
92
 }
..
..
@@ -102,8 +99,9 @@
102
99
 	idt_setup_apic_and_irq_gates();
103
100
 	lapic_assign_system_vectors();
104
101
 
105
-	if (!acpi_ioapic && !of_ioapic && nr_legacy_irqs())
106
-		setup_irq(2, &irq2);
107
-
108
-	irq_ctx_init(smp_processor_id());
102
+	if (!acpi_ioapic && !of_ioapic && nr_legacy_irqs()) {
103
+		/* IRQ2 is cascade interrupt to second interrupt controller */
104
+		if (request_irq(2, no_action, IRQF_NO_THREAD, "cascade", NULL))
105
+			pr_err("%s: request_irq() failed\n", "cascade");
106
+	}
109
107
 }