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2024-02-20 102a0743326a03cd1a1202ceda21e175b7d3575c

 kernel/arch/powerpc/kernel/dma-iommu.c
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@@ -6,7 +6,8 @@
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  * busses using the iommu infrastructure
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  */
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-#include <linux/export.h>
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+#include <linux/dma-direct.h>
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+#include <linux/pci.h>
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 #include <asm/iommu.h>
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 /*
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@@ -44,7 +45,7 @@
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 				     unsigned long attrs)
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 {
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 	return iommu_map_page(dev, get_iommu_table_base(dev), page, offset,
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-			      size, device_to_mask(dev), direction, attrs);
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+			      size, dma_get_mask(dev), direction, attrs);
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 }
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@@ -62,7 +63,7 @@
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 			    unsigned long attrs)
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 {
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 	return ppc_iommu_map_sg(dev, get_iommu_table_base(dev), sglist, nelems,
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-				device_to_mask(dev), direction, attrs);
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+				dma_get_mask(dev), direction, attrs);
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 }
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 static void dma_iommu_unmap_sg(struct device *dev, struct scatterlist *sglist,
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@@ -73,14 +74,29 @@
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 			   direction, attrs);
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 }
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+static bool dma_iommu_bypass_supported(struct device *dev, u64 mask)
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+{
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+	struct pci_dev *pdev = to_pci_dev(dev);
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+	struct pci_controller *phb = pci_bus_to_host(pdev->bus);
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+
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+	if (iommu_fixed_is_weak || !phb->controller_ops.iommu_bypass_supported)
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+		return false;
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+	return phb->controller_ops.iommu_bypass_supported(pdev, mask);
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+}
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+
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 /* We support DMA to/from any memory page via the iommu */
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 int dma_iommu_dma_supported(struct device *dev, u64 mask)
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 {
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 	struct iommu_table *tbl = get_iommu_table_base(dev);
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+	if (dev_is_pci(dev) && dma_iommu_bypass_supported(dev, mask)) {
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+		dev->dma_ops_bypass = true;
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+		dev_dbg(dev, "iommu: 64-bit OK, using fixed ops\n");
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+		return 1;
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+	}
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+
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 	if (!tbl) {
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-		dev_info(dev, "Warning: IOMMU dma not supported: mask 0x%08llx"
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-			", table unavailable\n", mask);
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+		dev_err(dev, "Warning: IOMMU dma not supported: mask 0x%08llx, table unavailable\n", mask);
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 		return 0;
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 	}
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@@ -89,14 +105,27 @@
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 		dev_info(dev, "mask: 0x%08llx, table offset: 0x%08lx\n",
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 				mask, tbl->it_offset << tbl->it_page_shift);
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 		return 0;
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-	} else
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-		return 1;
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+	}
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+
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+	dev_dbg(dev, "iommu: not 64-bit, using default ops\n");
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+	dev->dma_ops_bypass = false;
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+	return 1;
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 }
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-static u64 dma_iommu_get_required_mask(struct device *dev)
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+u64 dma_iommu_get_required_mask(struct device *dev)
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 {
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 	struct iommu_table *tbl = get_iommu_table_base(dev);
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 	u64 mask;
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+
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+	if (dev_is_pci(dev)) {
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+		u64 bypass_mask = dma_direct_get_required_mask(dev);
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+
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+		if (dma_iommu_dma_supported(dev, bypass_mask)) {
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+			dev_info(dev, "%s: returning bypass mask 0x%llx\n", __func__, bypass_mask);
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+			return bypass_mask;
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+		}
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+	}
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+
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 	if (!tbl)
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 		return 0;
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@@ -107,21 +136,17 @@
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 	return mask;
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 }
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-int dma_iommu_mapping_error(struct device *dev, dma_addr_t dma_addr)
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-{
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-	return dma_addr == IOMMU_MAPPING_ERROR;
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-}
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-
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-struct dma_map_ops dma_iommu_ops = {
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+const struct dma_map_ops dma_iommu_ops = {
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 	.alloc			= dma_iommu_alloc_coherent,
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 	.free			= dma_iommu_free_coherent,
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-	.mmap			= dma_nommu_mmap_coherent,
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 	.map_sg			= dma_iommu_map_sg,
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 	.unmap_sg		= dma_iommu_unmap_sg,
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 	.dma_supported		= dma_iommu_dma_supported,
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 	.map_page		= dma_iommu_map_page,
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 	.unmap_page		= dma_iommu_unmap_page,
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 	.get_required_mask	= dma_iommu_get_required_mask,
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-	.mapping_error		= dma_iommu_mapping_error,
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+	.mmap			= dma_common_mmap,
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+	.get_sgtable		= dma_common_get_sgtable,
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+	.alloc_pages		= dma_common_alloc_pages,
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+	.free_pages		= dma_common_free_pages,
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 };
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-EXPORT_SYMBOL(dma_iommu_ops);