add new system file

hc

2024-02-20 102a0743326a03cd1a1202ceda21e175b7d3575c

 kernel/arch/powerpc/include/asm/xive.h
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@@ -1,13 +1,11 @@
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+/* SPDX-License-Identifier: GPL-2.0-or-later */
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 /*
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  * Copyright 2016,2017 IBM Corporation.
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- *
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- * This program is free software; you can redistribute it and/or
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- * modify it under the terms of the GNU General Public License
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- * as published by the Free Software Foundation; either version
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- * 2 of the License, or (at your option) any later version.
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  */
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 #ifndef _ASM_POWERPC_XIVE_H
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 #define _ASM_POWERPC_XIVE_H
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+
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+#include <asm/opal-api.h>
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 #define XIVE_INVALID_VP	0xffffffff
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11
 
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@@ -23,6 +21,7 @@
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  * same offset regardless of where the code is executing
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  */
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 extern void __iomem *xive_tima;
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+extern unsigned long xive_tima_os;
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 /*
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  * Offset in the TM area of our current execution level (provided by
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@@ -49,7 +48,15 @@
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 	/* Setup/used by frontend */
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 	int target;
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+	/*
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+	 * saved_p means that there is a queue entry for this interrupt
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+	 * in some CPU's queue (not including guest vcpu queues), even
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+	 * if P is not set in the source ESB.
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+	 * stale_p means that there is no queue entry for this interrupt
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+	 * in some CPU's queue, even if P is set in the source ESB.
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+	 */
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 	bool saved_p;
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+	bool stale_p;
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 };
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 #define XIVE_IRQ_FLAG_STORE_EOI	0x01
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 #define XIVE_IRQ_FLAG_LSI	0x02
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@@ -73,6 +80,8 @@
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 	u32			esc_irq;
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 	atomic_t		count;
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 	atomic_t		pending_count;
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+	u64			guest_qaddr;
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+	u32			guest_qshift;
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 };
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 /* Global enable flags for the XIVE support */
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@@ -80,40 +89,61 @@
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 static inline bool xive_enabled(void) { return __xive_enabled; }
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-extern bool xive_spapr_init(void);
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-extern bool xive_native_init(void);
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-extern void xive_smp_probe(void);
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-extern int  xive_smp_prepare_cpu(unsigned int cpu);
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-extern void xive_smp_setup_cpu(void);
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-extern void xive_smp_disable_cpu(void);
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-extern void xive_teardown_cpu(void);
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-extern void xive_shutdown(void);
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-extern void xive_flush_interrupt(void);
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+bool xive_spapr_init(void);
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+bool xive_native_init(void);
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+void xive_smp_probe(void);
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+int  xive_smp_prepare_cpu(unsigned int cpu);
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+void xive_smp_setup_cpu(void);
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+void xive_smp_disable_cpu(void);
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+void xive_teardown_cpu(void);
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+void xive_shutdown(void);
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+void xive_flush_interrupt(void);
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 /* xmon hook */
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-extern void xmon_xive_do_dump(int cpu);
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+void xmon_xive_do_dump(int cpu);
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+int xmon_xive_get_irq_config(u32 hw_irq, struct irq_data *d);
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 /* APIs used by KVM */
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-extern u32 xive_native_default_eq_shift(void);
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-extern u32 xive_native_alloc_vp_block(u32 max_vcpus);
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-extern void xive_native_free_vp_block(u32 vp_base);
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-extern int xive_native_populate_irq_data(u32 hw_irq,
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-					 struct xive_irq_data *data);
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-extern void xive_cleanup_irq_data(struct xive_irq_data *xd);
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-extern u32 xive_native_alloc_irq(void);
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-extern void xive_native_free_irq(u32 irq);
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-extern int xive_native_configure_irq(u32 hw_irq, u32 target, u8 prio, u32 sw_irq);
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+u32 xive_native_default_eq_shift(void);
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+u32 xive_native_alloc_vp_block(u32 max_vcpus);
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+void xive_native_free_vp_block(u32 vp_base);
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+int xive_native_populate_irq_data(u32 hw_irq,
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+				  struct xive_irq_data *data);
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+void xive_cleanup_irq_data(struct xive_irq_data *xd);
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+void xive_native_free_irq(u32 irq);
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+int xive_native_configure_irq(u32 hw_irq, u32 target, u8 prio, u32 sw_irq);
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-extern int xive_native_configure_queue(u32 vp_id, struct xive_q *q, u8 prio,
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-				       __be32 *qpage, u32 order, bool can_escalate);
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-extern void xive_native_disable_queue(u32 vp_id, struct xive_q *q, u8 prio);
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+int xive_native_configure_queue(u32 vp_id, struct xive_q *q, u8 prio,
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+				__be32 *qpage, u32 order, bool can_escalate);
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+void xive_native_disable_queue(u32 vp_id, struct xive_q *q, u8 prio);
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-extern void xive_native_sync_source(u32 hw_irq);
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-extern bool is_xive_irq(struct irq_chip *chip);
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-extern int xive_native_enable_vp(u32 vp_id, bool single_escalation);
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-extern int xive_native_disable_vp(u32 vp_id);
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-extern int xive_native_get_vp_info(u32 vp_id, u32 *out_cam_id, u32 *out_chip_id);
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-extern bool xive_native_has_single_escalation(void);
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+void xive_native_sync_source(u32 hw_irq);
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+void xive_native_sync_queue(u32 hw_irq);
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+bool is_xive_irq(struct irq_chip *chip);
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+int xive_native_enable_vp(u32 vp_id, bool single_escalation);
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+int xive_native_disable_vp(u32 vp_id);
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+int xive_native_get_vp_info(u32 vp_id, u32 *out_cam_id, u32 *out_chip_id);
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+bool xive_native_has_single_escalation(void);
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+
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+int xive_native_get_queue_info(u32 vp_id, uint32_t prio,
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+			       u64 *out_qpage,
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+			       u64 *out_qsize,
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+			       u64 *out_qeoi_page,
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+			       u32 *out_escalate_irq,
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+			       u64 *out_qflags);
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+
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+int xive_native_get_queue_state(u32 vp_id, uint32_t prio, u32 *qtoggle,
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+				u32 *qindex);
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+int xive_native_set_queue_state(u32 vp_id, uint32_t prio, u32 qtoggle,
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+				u32 qindex);
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+int xive_native_get_vp_state(u32 vp_id, u64 *out_state);
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+bool xive_native_has_queue_state_support(void);
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+extern u32 xive_native_alloc_irq_on_chip(u32 chip_id);
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+
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+static inline u32 xive_native_alloc_irq(void)
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+{
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+	return xive_native_alloc_irq_on_chip(OPAL_XIVE_ANY_CHIP);
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+}
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 #else
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@@ -125,7 +155,6 @@
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 static inline int  xive_smp_prepare_cpu(unsigned int cpu) { return -EINVAL; }
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 static inline void xive_smp_setup_cpu(void) { }
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 static inline void xive_smp_disable_cpu(void) { }
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-static inline void xive_kexec_teardown_cpu(int secondary) { }
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 static inline void xive_shutdown(void) { }
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 static inline void xive_flush_interrupt(void) { }
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