add new system file

hc

2024-02-20 102a0743326a03cd1a1202ceda21e175b7d3575c

 kernel/arch/nds32/Kconfig.cpu
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+# SPDX-License-Identifier: GPL-2.0-only
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 comment "Processor Features"
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 config CPU_BIG_ENDIAN
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 config CPU_LITTLE_ENDIAN
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 	bool "Little endian"
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 	default y
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+
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+config FPU
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+	bool "FPU support"
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+	default n
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+	help
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+	  If FPU ISA is used in user space, this configuration shall be Y to
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+          enable required support in kernel such as fpu context switch and
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+          fpu exception handler.
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+
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+	  If no FPU ISA is used in user space, say N.
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+
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+config LAZY_FPU
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+	bool "lazy FPU support"
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+	depends on FPU
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+	default y
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+	help
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+	  Say Y here to enable the lazy FPU scheme. The lazy FPU scheme can
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+          enhance system performance by reducing the context switch
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+	  frequency of the FPU register.
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+	  For normal case, say Y.
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+
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+config SUPPORT_DENORMAL_ARITHMETIC
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+	bool "Denormal arithmetic support"
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+	depends on FPU
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+	default n
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+	help
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+	  Say Y here to enable arithmetic of denormalized number. Enabling
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+	  this feature can enhance the precision for tininess number.
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+	  However, performance loss in float point calculations is
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+	  possibly significant due to additional FPU exception.
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+
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+	  If the calculated tolerance for tininess number is not critical,
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+	  say N to prevent performance loss.
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 config HWZOL
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 	bool "hardware zero overhead loop support"
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 	  the cache aliasing issue. The rest cpus(N13, N10 and D10) are
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 	  implemented as VIPT data cache. It may cause the cache aliasing issue
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 	  if its cache way size is larger than page size. You can specify the
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-	  CPU type direcly or choose CPU_V3 if unsure.
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+	  CPU type directly or choose CPU_V3 if unsure.
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           A kernel built for N10 is able to run on N15, D15, N13, N10 or D10.
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           A kernel built for N15 is able to run on N15 or D15.
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 	  Say Y here to enable L2 cache if your SoC are integrated with L2CC.
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 	  If unsure, say N.
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+config HW_PRE
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+	bool "Enable hardware prefetcher"
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+	default y
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+	help
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+	  Say Y here to enable hardware prefetcher feature.
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+	  Only when CPU_VER.REV >= 0x09 can support.
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+
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 menu "Memory configuration"
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 choice