add new system file

hc

2024-02-20 102a0743326a03cd1a1202ceda21e175b7d3575c

 kernel/arch/mips/pci/pci-rt2880.c
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@@ -1,3 +1,4 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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 /*
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  *  Ralink RT288x SoC PCI register definitions
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  *
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@@ -5,10 +6,6 @@
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  *  Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
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  *
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  *  Parts of this file are based on Ralink's 2.6.21 BSP
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- *
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- *  This program is free software; you can redistribute it and/or modify it
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- *  under the terms of the GNU General Public License version 2 as published
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- *  by the Free Software Foundation.
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  */
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 #include <linux/delay.h>
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@@ -208,7 +205,7 @@
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 {
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 	void __iomem *io_map_base;
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-	rt2880_pci_base = ioremap_nocache(RT2880_PCI_BASE, PAGE_SIZE);
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+	rt2880_pci_base = ioremap(RT2880_PCI_BASE, PAGE_SIZE);
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 	io_map_base = ioremap(RT2880_PCI_IO_BASE, RT2880_PCI_IO_SIZE);
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 	rt2880_pci_controller.io_map_base = (unsigned long) io_map_base;
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@@ -233,6 +230,8 @@
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 	rt2880_pci_write_u32(PCI_BASE_ADDRESS_0, 0x08000000);
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 	(void) rt2880_pci_read_u32(PCI_BASE_ADDRESS_0);
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+	rt2880_pci_controller.of_node = pdev->dev.of_node;
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+
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 	register_pci_controller(&rt2880_pci_controller);
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 	return 0;
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 }