.. | .. |
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50 | 50 | insn_beq, insn_beql, insn_bgez, insn_bgezl, insn_bgtz, insn_blez, |
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51 | 51 | insn_bltz, insn_bltzl, insn_bne, insn_break, insn_cache, insn_cfc1, |
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52 | 52 | insn_cfcmsa, insn_ctc1, insn_ctcmsa, insn_daddiu, insn_daddu, insn_ddivu, |
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53 | | - insn_di, insn_dins, insn_dinsm, insn_dinsu, insn_divu, insn_dmfc0, |
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54 | | - insn_dmtc0, insn_dmultu, insn_drotr, insn_drotr32, insn_dsbh, insn_dshd, |
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55 | | - insn_dsll, insn_dsll32, insn_dsllv, insn_dsra, insn_dsra32, insn_dsrav, |
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56 | | - insn_dsrl, insn_dsrl32, insn_dsrlv, insn_dsubu, insn_eret, insn_ext, |
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57 | | - insn_ins, insn_j, insn_jal, insn_jalr, insn_jr, insn_lb, insn_lbu, |
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58 | | - insn_ld, insn_lddir, insn_ldpte, insn_ldx, insn_lh, insn_lhu, |
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59 | | - insn_ll, insn_lld, insn_lui, insn_lw, insn_lwu, insn_lwx, insn_mfc0, |
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60 | | - insn_mfhc0, insn_mfhi, insn_mflo, insn_movn, insn_movz, insn_mtc0, |
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61 | | - insn_mthc0, insn_mthi, insn_mtlo, insn_mul, insn_multu, insn_nor, |
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62 | | - insn_or, insn_ori, insn_pref, insn_rfe, insn_rotr, insn_sb, |
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63 | | - insn_sc, insn_scd, insn_sd, insn_sh, insn_sll, insn_sllv, |
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64 | | - insn_slt, insn_slti, insn_sltiu, insn_sltu, insn_sra, insn_srl, |
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65 | | - insn_srlv, insn_subu, insn_sw, insn_sync, insn_syscall, insn_tlbp, |
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66 | | - insn_tlbr, insn_tlbwi, insn_tlbwr, insn_wait, insn_wsbh, insn_xor, |
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67 | | - insn_xori, insn_yield, |
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| 53 | + insn_ddivu_r6, insn_di, insn_dins, insn_dinsm, insn_dinsu, insn_divu, |
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| 54 | + insn_divu_r6, insn_dmfc0, insn_dmodu, insn_dmtc0, insn_dmultu, |
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| 55 | + insn_dmulu, insn_drotr, insn_drotr32, insn_dsbh, insn_dshd, insn_dsll, |
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| 56 | + insn_dsll32, insn_dsllv, insn_dsra, insn_dsra32, insn_dsrav, insn_dsrl, |
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| 57 | + insn_dsrl32, insn_dsrlv, insn_dsubu, insn_eret, insn_ext, insn_ins, |
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| 58 | + insn_j, insn_jal, insn_jalr, insn_jr, insn_lb, insn_lbu, insn_ld, |
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| 59 | + insn_lddir, insn_ldpte, insn_ldx, insn_lh, insn_lhu, insn_ll, insn_lld, |
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| 60 | + insn_lui, insn_lw, insn_lwu, insn_lwx, insn_mfc0, insn_mfhc0, insn_mfhi, |
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| 61 | + insn_mflo, insn_modu, insn_movn, insn_movz, insn_mtc0, insn_mthc0, |
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| 62 | + insn_mthi, insn_mtlo, insn_mul, insn_multu, insn_mulu, insn_nor, |
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| 63 | + insn_or, insn_ori, insn_pref, insn_rfe, insn_rotr, insn_sb, insn_sc, |
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| 64 | + insn_scd, insn_seleqz, insn_selnez, insn_sd, insn_sh, insn_sll, |
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| 65 | + insn_sllv, insn_slt, insn_slti, insn_sltiu, insn_sltu, insn_sra, |
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| 66 | + insn_srav, insn_srl, insn_srlv, insn_subu, insn_sw, insn_sync, |
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| 67 | + insn_syscall, insn_tlbp, insn_tlbr, insn_tlbwi, insn_tlbwr, insn_wait, |
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| 68 | + insn_wsbh, insn_xor, insn_xori, insn_yield, |
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68 | 69 | insn_invalid /* insn_invalid must be last */ |
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69 | 70 | }; |
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70 | 71 | |
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.. | .. |
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287 | 288 | I_u1u2(_ctc1) |
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288 | 289 | I_u2u1(_ctcmsa) |
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289 | 290 | I_u1u2(_ddivu) |
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| 291 | +I_u3u1u2(_ddivu_r6) |
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290 | 292 | I_u1u2u3(_dmfc0) |
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| 293 | +I_u3u1u2(_dmodu) |
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291 | 294 | I_u1u2u3(_dmtc0) |
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292 | 295 | I_u1u2(_dmultu) |
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| 296 | +I_u3u1u2(_dmulu) |
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293 | 297 | I_u2u1s3(_daddiu) |
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294 | 298 | I_u3u1u2(_daddu) |
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295 | 299 | I_u1(_di); |
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296 | 300 | I_u1u2(_divu) |
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| 301 | +I_u3u1u2(_divu_r6) |
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297 | 302 | I_u2u1(_dsbh); |
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298 | 303 | I_u2u1(_dshd); |
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299 | 304 | I_u2u1u3(_dsll) |
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.. | .. |
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327 | 332 | I_u2s3u1(_lwu) |
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328 | 333 | I_u1u2u3(_mfc0) |
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329 | 334 | I_u1u2u3(_mfhc0) |
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| 335 | +I_u3u1u2(_modu) |
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330 | 336 | I_u3u1u2(_movn) |
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331 | 337 | I_u3u1u2(_movz) |
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332 | 338 | I_u1(_mfhi) |
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.. | .. |
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337 | 343 | I_u1(_mtlo) |
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338 | 344 | I_u3u1u2(_mul) |
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339 | 345 | I_u1u2(_multu) |
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| 346 | +I_u3u1u2(_mulu) |
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340 | 347 | I_u3u1u2(_nor) |
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341 | 348 | I_u3u1u2(_or) |
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342 | 349 | I_u2u1u3(_ori) |
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.. | .. |
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345 | 352 | I_u2s3u1(_sc) |
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346 | 353 | I_u2s3u1(_scd) |
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347 | 354 | I_u2s3u1(_sd) |
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| 355 | +I_u3u1u2(_seleqz) |
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| 356 | +I_u3u1u2(_selnez) |
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348 | 357 | I_u2s3u1(_sh) |
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349 | 358 | I_u2u1u3(_sll) |
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350 | 359 | I_u3u2u1(_sllv) |
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.. | .. |
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353 | 362 | I_u2u1s3(_sltiu) |
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354 | 363 | I_u3u1u2(_sltu) |
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355 | 364 | I_u2u1u3(_sra) |
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| 365 | +I_u3u2u1(_srav) |
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356 | 366 | I_u2u1u3(_srl) |
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357 | 367 | I_u3u2u1(_srlv) |
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358 | 368 | I_u2u1u3(_rotr) |
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.. | .. |
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384 | 394 | void uasm_i_pref(u32 **buf, unsigned int a, signed int b, |
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385 | 395 | unsigned int c) |
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386 | 396 | { |
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387 | | - if (CAVIUM_OCTEON_DCACHE_PREFETCH_WAR && a <= 24 && a != 5) |
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| 397 | + if (OCTEON_IS_MODEL(OCTEON_CN6XXX) && a <= 24 && a != 5) |
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388 | 398 | /* |
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389 | 399 | * As per erratum Core-14449, replace prefetches 0-4, |
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390 | 400 | * 6-24 with 'pref 28'. |
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