add new system file

hc

2024-02-20 102a0743326a03cd1a1202ceda21e175b7d3575c

 kernel/arch/mips/kernel/pm-cps.c
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@@ -1,11 +1,7 @@
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+// SPDX-License-Identifier: GPL-2.0-or-later
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 /*
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  * Copyright (C) 2014 Imagination Technologies
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  * Author: Paul Burton <paul.burton@mips.com>
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- *
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- * This program is free software; you can redistribute it and/or modify it
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- * under the terms of the GNU General Public License as published by the
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- * Free Software Foundation;  either version 2 of the  License, or (at your
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- * option) any later version.
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  */
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 #include <linux/cpuhotplug.h>
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@@ -311,7 +307,7 @@
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 	}
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 	/* Barrier ensuring previous cache invalidates are complete */
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-	uasm_i_sync(pp, STYPE_SYNC);
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+	uasm_i_sync(pp, __SYNC_full);
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 	uasm_i_ehb(pp);
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 	/* Check whether the pipeline stalled due to the FSB being full */
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@@ -401,7 +397,7 @@
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 	if (coupled_coherence) {
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 		/* Increment ready_count */
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-		uasm_i_sync(&p, STYPE_SYNC_MB);
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+		uasm_i_sync(&p, __SYNC_mb);
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 		uasm_build_label(&l, p, lbl_incready);
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 		uasm_i_ll(&p, t1, 0, r_nc_count);
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 		uasm_i_addiu(&p, t2, t1, 1);
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@@ -410,7 +406,7 @@
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 		uasm_i_addiu(&p, t1, t1, 1);
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 		/* Barrier ensuring all CPUs see the updated r_nc_count value */
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-		uasm_i_sync(&p, STYPE_SYNC_MB);
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+		uasm_i_sync(&p, __SYNC_mb);
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 		/*
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 		 * If this is the last VPE to become ready for non-coherence
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@@ -477,7 +473,7 @@
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 			      Index_Writeback_Inv_D, lbl_flushdcache);
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 	/* Barrier ensuring previous cache invalidates are complete */
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-	uasm_i_sync(&p, STYPE_SYNC);
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+	uasm_i_sync(&p, __SYNC_full);
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 	uasm_i_ehb(&p);
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 	if (mips_cm_revision() < CM_REV_CM3) {
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@@ -491,7 +487,7 @@
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 		uasm_i_lw(&p, t0, 0, r_pcohctl);
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 		/* Barrier to ensure write to coherence control is complete */
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-		uasm_i_sync(&p, STYPE_SYNC);
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+		uasm_i_sync(&p, __SYNC_full);
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 		uasm_i_ehb(&p);
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 	}
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@@ -538,7 +534,7 @@
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 		}
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 		/* Barrier to ensure write to CPC command is complete */
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-		uasm_i_sync(&p, STYPE_SYNC);
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+		uasm_i_sync(&p, __SYNC_full);
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 		uasm_i_ehb(&p);
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 	}
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@@ -576,13 +572,13 @@
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 	uasm_i_lw(&p, t0, 0, r_pcohctl);
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 	/* Barrier to ensure write to coherence control is complete */
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-	uasm_i_sync(&p, STYPE_SYNC);
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+	uasm_i_sync(&p, __SYNC_full);
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 	uasm_i_ehb(&p);
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 	if (coupled_coherence && (state == CPS_PM_NC_WAIT)) {
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 		/* Decrement ready_count */
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 		uasm_build_label(&l, p, lbl_decready);
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-		uasm_i_sync(&p, STYPE_SYNC_MB);
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+		uasm_i_sync(&p, __SYNC_mb);
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 		uasm_i_ll(&p, t1, 0, r_nc_count);
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 		uasm_i_addiu(&p, t2, t1, -1);
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 		uasm_i_sc(&p, t2, 0, r_nc_count);
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@@ -590,7 +586,7 @@
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 		uasm_i_andi(&p, v0, t1, (1 << fls(smp_num_siblings)) - 1);
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 		/* Barrier ensuring all CPUs see the updated r_nc_count value */
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-		uasm_i_sync(&p, STYPE_SYNC_MB);
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+		uasm_i_sync(&p, __SYNC_mb);
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 	}
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 	if (coupled_coherence && (state == CPS_PM_CLOCK_GATED)) {
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@@ -612,7 +608,7 @@
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 		uasm_build_label(&l, p, lbl_secondary_cont);
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 		/* Barrier ensuring all CPUs see the updated r_nc_count value */
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-		uasm_i_sync(&p, STYPE_SYNC_MB);
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+		uasm_i_sync(&p, __SYNC_mb);
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 	}
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 	/* The core is coherent, time to return to C code */