.. | .. |
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19 | 19 | #include <asm/thread_info.h> |
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20 | 20 | #include <asm/war.h> |
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21 | 21 | |
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22 | | -#ifndef CONFIG_PREEMPT |
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| 22 | +#ifndef CONFIG_PREEMPTION |
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23 | 23 | #define resume_kernel restore_all |
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24 | 24 | #else |
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25 | 25 | #define __ret_from_irq ret_from_exception |
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.. | .. |
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27 | 27 | |
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28 | 28 | .text |
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29 | 29 | .align 5 |
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30 | | -#ifndef CONFIG_PREEMPT |
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| 30 | +#ifndef CONFIG_PREEMPTION |
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31 | 31 | FEXPORT(ret_from_exception) |
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32 | 32 | local_irq_disable # preempt stop |
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33 | 33 | b __ret_from_irq |
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.. | .. |
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53 | 53 | bnez t0, work_pending |
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54 | 54 | j restore_all |
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55 | 55 | |
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56 | | -#ifdef CONFIG_PREEMPT |
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| 56 | +#ifdef CONFIG_PREEMPTION |
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57 | 57 | resume_kernel: |
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58 | 58 | local_irq_disable |
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59 | 59 | lw t0, TI_PRE_COUNT($28) |
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60 | 60 | bnez t0, restore_all |
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61 | | -need_resched: |
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62 | 61 | LONG_L t0, TI_FLAGS($28) |
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63 | 62 | andi t1, t0, _TIF_NEED_RESCHED |
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64 | 63 | beqz t1, restore_all |
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65 | 64 | LONG_L t0, PT_STATUS(sp) # Interrupts off? |
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66 | 65 | andi t0, 1 |
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67 | 66 | beqz t0, restore_all |
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68 | | - jal preempt_schedule_irq |
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69 | | - b need_resched |
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| 67 | + PTR_LA ra, restore_all |
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| 68 | + j preempt_schedule_irq |
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70 | 69 | #endif |
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71 | 70 | |
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72 | 71 | FEXPORT(ret_from_kernel_thread) |
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.. | .. |
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170 | 169 | jal syscall_trace_leave |
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171 | 170 | b resume_userspace |
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172 | 171 | |
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173 | | -#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6) || \ |
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174 | | - defined(CONFIG_MIPS_MT) |
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| 172 | +#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR5) || \ |
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| 173 | + defined(CONFIG_CPU_MIPSR6) || defined(CONFIG_MIPS_MT) |
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175 | 174 | |
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176 | 175 | /* |
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177 | 176 | * MIPS32R2 Instruction Hazard Barrier - must be called |
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.. | .. |
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184 | 183 | nop |
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185 | 184 | END(mips_ihb) |
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186 | 185 | |
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187 | | -#endif /* CONFIG_CPU_MIPSR2 or CONFIG_CPU_MIPSR6 or CONFIG_MIPS_MT */ |
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| 186 | +#endif /* CONFIG_CPU_MIPSR2 - CONFIG_CPU_MIPSR6 or CONFIG_MIPS_MT */ |
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