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2024-02-20 102a0743326a03cd1a1202ceda21e175b7d3575c

 kernel/arch/mips/kernel/csrc-r4k.c
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@@ -6,6 +6,7 @@
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  * Copyright (C) 2007 by Ralf Baechle
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  */
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 #include <linux/clocksource.h>
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+#include <linux/cpufreq.h>
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 #include <linux/init.h>
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 #include <linux/sched_clock.h>
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@@ -65,6 +66,45 @@
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 	return false;
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 }
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+#ifdef CONFIG_CPU_FREQ
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+
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+static bool __read_mostly r4k_clock_unstable;
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+
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+static void r4k_clocksource_unstable(char *reason)
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+{
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+	if (r4k_clock_unstable)
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+		return;
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+
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+	r4k_clock_unstable = true;
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+
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+	pr_info("R4K timer is unstable due to %s\n", reason);
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+
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+	clocksource_mark_unstable(&clocksource_mips);
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+}
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+
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+static int r4k_cpufreq_callback(struct notifier_block *nb,
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+				unsigned long val, void *data)
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+{
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+	if (val == CPUFREQ_POSTCHANGE)
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+		r4k_clocksource_unstable("CPU frequency change");
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+
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+	return 0;
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+}
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+
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+static struct notifier_block r4k_cpufreq_notifier = {
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+	.notifier_call  = r4k_cpufreq_callback,
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+};
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+
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+static int __init r4k_register_cpufreq_notifier(void)
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+{
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+	return cpufreq_register_notifier(&r4k_cpufreq_notifier,
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+					 CPUFREQ_TRANSITION_NOTIFIER);
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+
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+}
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+core_initcall(r4k_register_cpufreq_notifier);
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+
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+#endif /* !CONFIG_CPU_FREQ */
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+
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 int __init init_r4k_clocksource(void)
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 {
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 	if (!cpu_has_counter || !mips_hpt_frequency)
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@@ -78,7 +118,7 @@
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 	 * by the VDSO (HWREna is configured by configure_hwrena()).
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 	 */
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 	if (cpu_has_mips_r2_r6 && rdhwr_count_usable())
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-		clocksource_mips.archdata.vdso_clock_mode = VDSO_CLOCK_R4K;
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+		clocksource_mips.vdso_clock_mode = VDSO_CLOCKMODE_R4K;
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 	clocksource_register_hz(&clocksource_mips, mips_hpt_frequency);
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