add new system file

hc

2024-02-20 102a0743326a03cd1a1202ceda21e175b7d3575c

 kernel/arch/mips/ath79/setup.c
..
..
@@ -1,3 +1,4 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
1
2
 /*
2
3
  *  Atheros AR71XX/AR724X/AR913X specific setup
3
4
  *
..
..
@@ -6,33 +7,28 @@
6
7
  *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
7
8
  *
8
9
  *  Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
9
- *
10
- *  This program is free software; you can redistribute it and/or modify it
11
- *  under the terms of the GNU General Public License version 2 as published
12
- *  by the Free Software Foundation.
13
10
  */
14
11
 
15
12
 #include <linux/kernel.h>
16
13
 #include <linux/init.h>
17
-#include <linux/bootmem.h>
14
+#include <linux/io.h>
15
+#include <linux/memblock.h>
18
16
 #include <linux/err.h>
19
17
 #include <linux/clk.h>
20
-#include <linux/clk-provider.h>
18
+#include <linux/of_clk.h>
21
19
 #include <linux/of_fdt.h>
20
+#include <linux/irqchip.h>
22
21
 
23
22
 #include <asm/bootinfo.h>
24
23
 #include <asm/idle.h>
25
24
 #include <asm/time.h>		/* for mips_hpt_frequency */
26
25
 #include <asm/reboot.h>		/* for _machine_{restart,halt} */
27
-#include <asm/mips_machine.h>
28
26
 #include <asm/prom.h>
29
27
 #include <asm/fw/fw.h>
30
28
 
31
29
 #include <asm/mach-ath79/ath79.h>
32
30
 #include <asm/mach-ath79/ar71xx_regs.h>
33
31
 #include "common.h"
34
-#include "dev-common.h"
35
-#include "machtypes.h"
36
32
 
37
33
 #define ATH79_SYS_TYPE_LEN	64
38
34
 
..
..
@@ -156,8 +152,7 @@
156
152
 	case REV_ID_MAJOR_QCA9533_V2:
157
153
 		ver = 2;
158
154
 		ath79_soc_rev = 2;
159
-		/* drop through */
160
-
155
+		fallthrough;
161
156
 	case REV_ID_MAJOR_QCA9533:
162
157
 		ath79_soc = ATH79_SOC_QCA9533;
163
158
 		chip = "9533";
..
..
@@ -211,12 +206,6 @@
211
206
 	return ath79_sys_type;
212
207
 }
213
208
 
214
-int get_c0_perfcount_int(void)
215
-{
216
-	return ATH79_MISC_IRQ(5);
217
-}
218
-EXPORT_SYMBOL_GPL(get_c0_perfcount_int);
219
-
220
209
 unsigned int get_c0_compare_int(void)
221
210
 {
222
211
 	return CP0_LEGACY_COMPARE_IRQ;
..
..
@@ -235,25 +224,21 @@
235
224
 	else if (fw_passed_dtb)
236
225
 		__dt_setup_arch((void *)KSEG0ADDR(fw_passed_dtb));
237
226
 
238
-	if (mips_machtype != ATH79_MACH_GENERIC_OF) {
239
-		ath79_reset_base = ioremap_nocache(AR71XX_RESET_BASE,
240
-						   AR71XX_RESET_SIZE);
241
-		ath79_pll_base = ioremap_nocache(AR71XX_PLL_BASE,
242
-						 AR71XX_PLL_SIZE);
243
-		ath79_detect_sys_type();
244
-		ath79_ddr_ctrl_init();
227
+	ath79_reset_base = ioremap(AR71XX_RESET_BASE,
228
+					   AR71XX_RESET_SIZE);
229
+	ath79_pll_base = ioremap(AR71XX_PLL_BASE,
230
+					 AR71XX_PLL_SIZE);
231
+	ath79_detect_sys_type();
232
+	ath79_ddr_ctrl_init();
245
233
 
246
-		detect_memory_region(0, ATH79_MEM_SIZE_MIN, ATH79_MEM_SIZE_MAX);
234
+	detect_memory_region(0, ATH79_MEM_SIZE_MIN, ATH79_MEM_SIZE_MAX);
247
235
 
248
-		/* OF machines should use the reset driver */
249
-		_machine_restart = ath79_restart;
250
-	}
251
-
236
+	_machine_restart = ath79_restart;
252
237
 	_machine_halt = ath79_halt;
253
238
 	pm_power_off = ath79_halt;
254
239
 }
255
240
 
256
-static void __init ath79_of_plat_time_init(void)
241
+void __init plat_time_init(void)
257
242
 {
258
243
 	struct device_node *np;
259
244
 	struct clk *clk;
..
..
@@ -283,61 +268,12 @@
283
268
 	clk_put(clk);
284
269
 }
285
270
 
286
-void __init plat_time_init(void)
271
+void __init arch_init_irq(void)
287
272
 {
288
-	unsigned long cpu_clk_rate;
289
-	unsigned long ahb_clk_rate;
290
-	unsigned long ddr_clk_rate;
291
-	unsigned long ref_clk_rate;
292
-
293
-	if (IS_ENABLED(CONFIG_OF) && mips_machtype == ATH79_MACH_GENERIC_OF) {
294
-		ath79_of_plat_time_init();
295
-		return;
296
-	}
297
-
298
-	ath79_clocks_init();
299
-
300
-	cpu_clk_rate = ath79_get_sys_clk_rate("cpu");
301
-	ahb_clk_rate = ath79_get_sys_clk_rate("ahb");
302
-	ddr_clk_rate = ath79_get_sys_clk_rate("ddr");
303
-	ref_clk_rate = ath79_get_sys_clk_rate("ref");
304
-
305
-	pr_info("Clocks: CPU:%lu.%03luMHz, DDR:%lu.%03luMHz, AHB:%lu.%03luMHz, Ref:%lu.%03luMHz\n",
306
-		cpu_clk_rate / 1000000, (cpu_clk_rate / 1000) % 1000,
307
-		ddr_clk_rate / 1000000, (ddr_clk_rate / 1000) % 1000,
308
-		ahb_clk_rate / 1000000, (ahb_clk_rate / 1000) % 1000,
309
-		ref_clk_rate / 1000000, (ref_clk_rate / 1000) % 1000);
310
-
311
-	mips_hpt_frequency = cpu_clk_rate / 2;
273
+	irqchip_init();
312
274
 }
313
-
314
-static int __init ath79_setup(void)
315
-{
316
-	if  (mips_machtype == ATH79_MACH_GENERIC_OF)
317
-		return 0;
318
-
319
-	ath79_gpio_init();
320
-	ath79_register_uart();
321
-	ath79_register_wdt();
322
-
323
-	mips_machine_setup();
324
-
325
-	return 0;
326
-}
327
-
328
-arch_initcall(ath79_setup);
329
275
 
330
276
 void __init device_tree_init(void)
331
277
 {
332
278
 	unflatten_and_copy_device_tree();
333
279
 }
334
-
335
-MIPS_MACHINE(ATH79_MACH_GENERIC,
336
-	     "Generic",
337
-	     "Generic AR71XX/AR724X/AR913X based board",
338
-	     NULL);
339
-
340
-MIPS_MACHINE(ATH79_MACH_GENERIC_OF,
341
-	     "DTB",
342
-	     "Generic AR71XX/AR724X/AR913X based board (DT)",
343
-	     NULL);