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2024-02-20 102a0743326a03cd1a1202ceda21e175b7d3575c

 kernel/arch/mips/ath79/clock.c
..
..
@@ -1,3 +1,4 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
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2
 /*
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  *  Atheros AR71XX/AR724X/AR913X common routines
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  *
..
..
@@ -5,14 +6,11 @@
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  *  Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
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  *
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  *  Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
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- *
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- *  This program is free software; you can redistribute it and/or modify it
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- *  under the terms of the GNU General Public License version 2 as published
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- *  by the Free Software Foundation.
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  */
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10
 
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 #include <linux/kernel.h>
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 #include <linux/init.h>
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+#include <linux/io.h>
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 #include <linux/err.h>
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 #include <linux/clk.h>
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 #include <linux/clkdev.h>
..
..
@@ -26,7 +24,6 @@
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 #include <asm/mach-ath79/ath79.h>
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 #include <asm/mach-ath79/ar71xx_regs.h>
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 #include "common.h"
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-#include "machtypes.h"
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27
 
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 #define AR71XX_BASE_FREQ	40000000
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29
 #define AR724X_BASE_FREQ	40000000
..
..
@@ -37,24 +34,63 @@
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 	.clk_num = ARRAY_SIZE(clks),
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35
 };
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36
 
40
-static struct clk *__init ath79_add_sys_clkdev(
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-	const char *id, unsigned long rate)
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+static const char * const clk_names[ATH79_CLK_END] = {
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+	[ATH79_CLK_CPU] = "cpu",
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+	[ATH79_CLK_DDR] = "ddr",
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+	[ATH79_CLK_AHB] = "ahb",
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+	[ATH79_CLK_REF] = "ref",
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+	[ATH79_CLK_MDIO] = "mdio",
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+};
44
+
45
+static const char * __init ath79_clk_name(int type)
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46
 {
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-	struct clk *clk;
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-	int err;
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+	BUG_ON(type >= ARRAY_SIZE(clk_names) || !clk_names[type]);
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+	return clk_names[type];
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+}
45
50
 
46
-	clk = clk_register_fixed_rate(NULL, id, NULL, 0, rate);
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+static void __init __ath79_set_clk(int type, const char *name, struct clk *clk)
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+{
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 	if (IS_ERR(clk))
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-		panic("failed to allocate %s clock structure", id);
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+		panic("failed to allocate %s clock structure", clk_names[type]);
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55
 
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-	err = clk_register_clkdev(clk, id, NULL);
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-	if (err)
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-		panic("unable to register %s clock device", id);
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+	clks[type] = clk;
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+	clk_register_clkdev(clk, name, NULL);
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+}
53
59
 
60
+static struct clk * __init ath79_set_clk(int type, unsigned long rate)
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+{
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+	const char *name = ath79_clk_name(type);
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+	struct clk *clk;
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+
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+	clk = clk_register_fixed_rate(NULL, name, NULL, 0, rate);
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+	__ath79_set_clk(type, name, clk);
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67
 	return clk;
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68
 }
56
69
 
57
-static void __init ar71xx_clocks_init(void)
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+static struct clk * __init ath79_set_ff_clk(int type, const char *parent,
71
+					    unsigned int mult, unsigned int div)
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+{
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+	const char *name = ath79_clk_name(type);
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+	struct clk *clk;
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+
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+	clk = clk_register_fixed_factor(NULL, name, parent, 0, mult, div);
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+	__ath79_set_clk(type, name, clk);
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+	return clk;
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+}
80
+
81
+static unsigned long __init ath79_setup_ref_clk(unsigned long rate)
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+{
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+	struct clk *clk = clks[ATH79_CLK_REF];
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+
85
+	if (clk)
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+		rate = clk_get_rate(clk);
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+	else
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+		clk = ath79_set_clk(ATH79_CLK_REF, rate);
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+
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+	return rate;
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+}
92
+
93
+static void __init ar71xx_clocks_init(void __iomem *pll_base)
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 {
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 	unsigned long ref_rate;
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96
 	unsigned long cpu_rate;
..
..
@@ -64,9 +100,9 @@
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100
 	u32 freq;
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101
 	u32 div;
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102
 
67
-	ref_rate = AR71XX_BASE_FREQ;
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+	ref_rate = ath79_setup_ref_clk(AR71XX_BASE_FREQ);
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104
 
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-	pll = ath79_pll_rr(AR71XX_PLL_REG_CPU_CONFIG);
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+	pll = __raw_readl(pll_base + AR71XX_PLL_REG_CPU_CONFIG);
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106
 
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 	div = ((pll >> AR71XX_PLL_FB_SHIFT) & AR71XX_PLL_FB_MASK) + 1;
72
108
 	freq = div * ref_rate;
..
..
@@ -80,31 +116,17 @@
80
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 	div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2;
81
117
 	ahb_rate = cpu_rate / div;
82
118
 
83
-	ath79_add_sys_clkdev("ref", ref_rate);
84
-	clks[ATH79_CLK_CPU] = ath79_add_sys_clkdev("cpu", cpu_rate);
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-	clks[ATH79_CLK_DDR] = ath79_add_sys_clkdev("ddr", ddr_rate);
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-	clks[ATH79_CLK_AHB] = ath79_add_sys_clkdev("ahb", ahb_rate);
87
-
88
-	clk_add_alias("wdt", NULL, "ahb", NULL);
89
-	clk_add_alias("uart", NULL, "ahb", NULL);
119
+	ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
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+	ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
121
+	ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
90
122
 }
91
123
 
92
-static struct clk * __init ath79_reg_ffclk(const char *name,
93
-		const char *parent_name, unsigned int mult, unsigned int div)
124
+static void __init ar724x_clocks_init(void __iomem *pll_base)
94
125
 {
95
-	struct clk *clk;
96
-
97
-	clk = clk_register_fixed_factor(NULL, name, parent_name, 0, mult, div);
98
-	if (IS_ERR(clk))
99
-		panic("failed to allocate %s clock structure", name);
100
-
101
-	return clk;
102
-}
103
-
104
-static void __init ar724x_clk_init(struct clk *ref_clk, void __iomem *pll_base)
105
-{
106
-	u32 pll;
107
126
 	u32 mult, div, ddr_div, ahb_div;
127
+	u32 pll;
128
+
129
+	ath79_setup_ref_clk(AR71XX_BASE_FREQ);
108
130
 
109
131
 	pll = __raw_readl(pll_base + AR724X_PLL_REG_CPU_CONFIG);
110
132
 
..
..
@@ -114,30 +136,14 @@
114
136
 	ddr_div = ((pll >> AR724X_DDR_DIV_SHIFT) & AR724X_DDR_DIV_MASK) + 1;
115
137
 	ahb_div = (((pll >> AR724X_AHB_DIV_SHIFT) & AR724X_AHB_DIV_MASK) + 1) * 2;
116
138
 
117
-	clks[ATH79_CLK_CPU] = ath79_reg_ffclk("cpu", "ref", mult, div);
118
-	clks[ATH79_CLK_DDR] = ath79_reg_ffclk("ddr", "ref", mult, div * ddr_div);
119
-	clks[ATH79_CLK_AHB] = ath79_reg_ffclk("ahb", "ref", mult, div * ahb_div);
139
+	ath79_set_ff_clk(ATH79_CLK_CPU, "ref", mult, div);
140
+	ath79_set_ff_clk(ATH79_CLK_DDR, "ref", mult, div * ddr_div);
141
+	ath79_set_ff_clk(ATH79_CLK_AHB, "ref", mult, div * ahb_div);
120
142
 }
121
143
 
122
-static void __init ar724x_clocks_init(void)
144
+static void __init ar933x_clocks_init(void __iomem *pll_base)
123
145
 {
124
-	struct clk *ref_clk;
125
-
126
-	ref_clk = ath79_add_sys_clkdev("ref", AR724X_BASE_FREQ);
127
-
128
-	ar724x_clk_init(ref_clk, ath79_pll_base);
129
-
130
-	/* just make happy plat_time_init() from arch/mips/ath79/setup.c */
131
-	clk_register_clkdev(clks[ATH79_CLK_CPU], "cpu", NULL);
132
-	clk_register_clkdev(clks[ATH79_CLK_DDR], "ddr", NULL);
133
-	clk_register_clkdev(clks[ATH79_CLK_AHB], "ahb", NULL);
134
-
135
-	clk_add_alias("wdt", NULL, "ahb", NULL);
136
-	clk_add_alias("uart", NULL, "ahb", NULL);
137
-}
138
-
139
-static void __init ar9330_clk_init(struct clk *ref_clk, void __iomem *pll_base)
140
-{
146
+	unsigned long ref_rate;
141
147
 	u32 clock_ctrl;
142
148
 	u32 ref_div;
143
149
 	u32 ninit_mul;
..
..
@@ -146,6 +152,15 @@
146
152
 	u32 cpu_div;
147
153
 	u32 ddr_div;
148
154
 	u32 ahb_div;
155
+	u32 t;
156
+
157
+	t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
158
+	if (t & AR933X_BOOTSTRAP_REF_CLK_40)
159
+		ref_rate = (40 * 1000 * 1000);
160
+	else
161
+		ref_rate = (25 * 1000 * 1000);
162
+
163
+	ath79_setup_ref_clk(ref_rate);
149
164
 
150
165
 	clock_ctrl = __raw_readl(pll_base + AR933X_PLL_CLOCK_CTRL_REG);
151
166
 	if (clock_ctrl & AR933X_PLL_CLOCK_CTRL_BYPASS) {
..
..
@@ -186,37 +201,12 @@
186
201
 		     AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK) + 1;
187
202
 	}
188
203
 
189
-	clks[ATH79_CLK_CPU] = ath79_reg_ffclk("cpu", "ref",
190
-					ninit_mul, ref_div * out_div * cpu_div);
191
-	clks[ATH79_CLK_DDR] = ath79_reg_ffclk("ddr", "ref",
192
-					ninit_mul, ref_div * out_div * ddr_div);
193
-	clks[ATH79_CLK_AHB] = ath79_reg_ffclk("ahb", "ref",
194
-					ninit_mul, ref_div * out_div * ahb_div);
195
-}
196
-
197
-static void __init ar933x_clocks_init(void)
198
-{
199
-	struct clk *ref_clk;
200
-	unsigned long ref_rate;
201
-	u32 t;
202
-
203
-	t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
204
-	if (t & AR933X_BOOTSTRAP_REF_CLK_40)
205
-		ref_rate = (40 * 1000 * 1000);
206
-	else
207
-		ref_rate = (25 * 1000 * 1000);
208
-
209
-	ref_clk = ath79_add_sys_clkdev("ref", ref_rate);
210
-
211
-	ar9330_clk_init(ref_clk, ath79_pll_base);
212
-
213
-	/* just make happy plat_time_init() from arch/mips/ath79/setup.c */
214
-	clk_register_clkdev(clks[ATH79_CLK_CPU], "cpu", NULL);
215
-	clk_register_clkdev(clks[ATH79_CLK_DDR], "ddr", NULL);
216
-	clk_register_clkdev(clks[ATH79_CLK_AHB], "ahb", NULL);
217
-
218
-	clk_add_alias("wdt", NULL, "ahb", NULL);
219
-	clk_add_alias("uart", NULL, "ref", NULL);
204
+	ath79_set_ff_clk(ATH79_CLK_CPU, "ref", ninit_mul,
205
+			 ref_div * out_div * cpu_div);
206
+	ath79_set_ff_clk(ATH79_CLK_DDR, "ref", ninit_mul,
207
+			 ref_div * out_div * ddr_div);
208
+	ath79_set_ff_clk(ATH79_CLK_AHB, "ref", ninit_mul,
209
+			 ref_div * out_div * ahb_div);
220
210
 }
221
211
 
222
212
 static u32 __init ar934x_get_pll_freq(u32 ref, u32 ref_div, u32 nint, u32 nfrac,
..
..
@@ -239,7 +229,7 @@
239
229
 	return ret;
240
230
 }
241
231
 
242
-static void __init ar934x_clocks_init(void)
232
+static void __init ar934x_clocks_init(void __iomem *pll_base)
243
233
 {
244
234
 	unsigned long ref_rate;
245
235
 	unsigned long cpu_rate;
..
..
@@ -258,6 +248,8 @@
258
248
 	else
259
249
 		ref_rate = 25 * 1000 * 1000;
260
250
 
251
+	ref_rate = ath79_setup_ref_clk(ref_rate);
252
+
261
253
 	pll = __raw_readl(dpll_base + AR934X_SRIF_CPU_DPLL2_REG);
262
254
 	if (pll & AR934X_SRIF_DPLL2_LOCAL_PLL) {
263
255
 		out_div = (pll >> AR934X_SRIF_DPLL2_OUTDIV_SHIFT) &
..
..
@@ -270,7 +262,7 @@
270
262
 			  AR934X_SRIF_DPLL1_REFDIV_MASK;
271
263
 		frac = 1 << 18;
272
264
 	} else {
273
-		pll = ath79_pll_rr(AR934X_PLL_CPU_CONFIG_REG);
265
+		pll = __raw_readl(pll_base + AR934X_PLL_CPU_CONFIG_REG);
274
266
 		out_div = (pll >> AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
275
267
 			AR934X_PLL_CPU_CONFIG_OUTDIV_MASK;
276
268
 		ref_div = (pll >> AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
..
..
@@ -297,7 +289,7 @@
297
289
 			  AR934X_SRIF_DPLL1_REFDIV_MASK;
298
290
 		frac = 1 << 18;
299
291
 	} else {
300
-		pll = ath79_pll_rr(AR934X_PLL_DDR_CONFIG_REG);
292
+		pll = __raw_readl(pll_base + AR934X_PLL_DDR_CONFIG_REG);
301
293
 		out_div = (pll >> AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
302
294
 			  AR934X_PLL_DDR_CONFIG_OUTDIV_MASK;
303
295
 		ref_div = (pll >> AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
..
..
@@ -312,7 +304,7 @@
312
304
 	ddr_pll = ar934x_get_pll_freq(ref_rate, ref_div, nint,
313
305
 				      nfrac, frac, out_div);
314
306
 
315
-	clk_ctrl = ath79_pll_rr(AR934X_PLL_CPU_DDR_CLK_CTRL_REG);
307
+	clk_ctrl = __raw_readl(pll_base + AR934X_PLL_CPU_DDR_CLK_CTRL_REG);
316
308
 
317
309
 	postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT) &
318
310
 		  AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK;
..
..
@@ -344,18 +336,18 @@
344
336
 	else
345
337
 		ahb_rate = cpu_pll / (postdiv + 1);
346
338
 
347
-	ath79_add_sys_clkdev("ref", ref_rate);
348
-	clks[ATH79_CLK_CPU] = ath79_add_sys_clkdev("cpu", cpu_rate);
349
-	clks[ATH79_CLK_DDR] = ath79_add_sys_clkdev("ddr", ddr_rate);
350
-	clks[ATH79_CLK_AHB] = ath79_add_sys_clkdev("ahb", ahb_rate);
339
+	ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
340
+	ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
341
+	ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
351
342
 
352
-	clk_add_alias("wdt", NULL, "ref", NULL);
353
-	clk_add_alias("uart", NULL, "ref", NULL);
343
+	clk_ctrl = __raw_readl(pll_base + AR934X_PLL_SWITCH_CLOCK_CONTROL_REG);
344
+	if (clk_ctrl & AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL)
345
+		ath79_set_clk(ATH79_CLK_MDIO, 100 * 1000 * 1000);
354
346
 
355
347
 	iounmap(dpll_base);
356
348
 }
357
349
 
358
-static void __init qca953x_clocks_init(void)
350
+static void __init qca953x_clocks_init(void __iomem *pll_base)
359
351
 {
360
352
 	unsigned long ref_rate;
361
353
 	unsigned long cpu_rate;
..
..
@@ -371,7 +363,9 @@
371
363
 	else
372
364
 		ref_rate = 25 * 1000 * 1000;
373
365
 
374
-	pll = ath79_pll_rr(QCA953X_PLL_CPU_CONFIG_REG);
366
+	ref_rate = ath79_setup_ref_clk(ref_rate);
367
+
368
+	pll = __raw_readl(pll_base + QCA953X_PLL_CPU_CONFIG_REG);
375
369
 	out_div = (pll >> QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
376
370
 		  QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK;
377
371
 	ref_div = (pll >> QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
..
..
@@ -385,7 +379,7 @@
385
379
 	cpu_pll += frac * (ref_rate >> 6) / ref_div;
386
380
 	cpu_pll /= (1 << out_div);
387
381
 
388
-	pll = ath79_pll_rr(QCA953X_PLL_DDR_CONFIG_REG);
382
+	pll = __raw_readl(pll_base + QCA953X_PLL_DDR_CONFIG_REG);
389
383
 	out_div = (pll >> QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
390
384
 		  QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK;
391
385
 	ref_div = (pll >> QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
..
..
@@ -399,7 +393,7 @@
399
393
 	ddr_pll += frac * (ref_rate >> 6) / (ref_div << 4);
400
394
 	ddr_pll /= (1 << out_div);
401
395
 
402
-	clk_ctrl = ath79_pll_rr(QCA953X_PLL_CLK_CTRL_REG);
396
+	clk_ctrl = __raw_readl(pll_base + QCA953X_PLL_CLK_CTRL_REG);
403
397
 
404
398
 	postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
405
399
 		  QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
..
..
@@ -431,16 +425,12 @@
431
425
 	else
432
426
 		ahb_rate = cpu_pll / (postdiv + 1);
433
427
 
434
-	ath79_add_sys_clkdev("ref", ref_rate);
435
-	ath79_add_sys_clkdev("cpu", cpu_rate);
436
-	ath79_add_sys_clkdev("ddr", ddr_rate);
437
-	ath79_add_sys_clkdev("ahb", ahb_rate);
438
-
439
-	clk_add_alias("wdt", NULL, "ref", NULL);
440
-	clk_add_alias("uart", NULL, "ref", NULL);
428
+	ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
429
+	ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
430
+	ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
441
431
 }
442
432
 
443
-static void __init qca955x_clocks_init(void)
433
+static void __init qca955x_clocks_init(void __iomem *pll_base)
444
434
 {
445
435
 	unsigned long ref_rate;
446
436
 	unsigned long cpu_rate;
..
..
@@ -456,7 +446,9 @@
456
446
 	else
457
447
 		ref_rate = 25 * 1000 * 1000;
458
448
 
459
-	pll = ath79_pll_rr(QCA955X_PLL_CPU_CONFIG_REG);
449
+	ref_rate = ath79_setup_ref_clk(ref_rate);
450
+
451
+	pll = __raw_readl(pll_base + QCA955X_PLL_CPU_CONFIG_REG);
460
452
 	out_div = (pll >> QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
461
453
 		  QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK;
462
454
 	ref_div = (pll >> QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
..
..
@@ -470,7 +462,7 @@
470
462
 	cpu_pll += frac * ref_rate / (ref_div * (1 << 6));
471
463
 	cpu_pll /= (1 << out_div);
472
464
 
473
-	pll = ath79_pll_rr(QCA955X_PLL_DDR_CONFIG_REG);
465
+	pll = __raw_readl(pll_base + QCA955X_PLL_DDR_CONFIG_REG);
474
466
 	out_div = (pll >> QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
475
467
 		  QCA955X_PLL_DDR_CONFIG_OUTDIV_MASK;
476
468
 	ref_div = (pll >> QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
..
..
@@ -484,7 +476,7 @@
484
476
 	ddr_pll += frac * ref_rate / (ref_div * (1 << 10));
485
477
 	ddr_pll /= (1 << out_div);
486
478
 
487
-	clk_ctrl = ath79_pll_rr(QCA955X_PLL_CLK_CTRL_REG);
479
+	clk_ctrl = __raw_readl(pll_base + QCA955X_PLL_CLK_CTRL_REG);
488
480
 
489
481
 	postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
490
482
 		  QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
..
..
@@ -516,16 +508,12 @@
516
508
 	else
517
509
 		ahb_rate = cpu_pll / (postdiv + 1);
518
510
 
519
-	ath79_add_sys_clkdev("ref", ref_rate);
520
-	clks[ATH79_CLK_CPU] = ath79_add_sys_clkdev("cpu", cpu_rate);
521
-	clks[ATH79_CLK_DDR] = ath79_add_sys_clkdev("ddr", ddr_rate);
522
-	clks[ATH79_CLK_AHB] = ath79_add_sys_clkdev("ahb", ahb_rate);
523
-
524
-	clk_add_alias("wdt", NULL, "ref", NULL);
525
-	clk_add_alias("uart", NULL, "ref", NULL);
511
+	ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
512
+	ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
513
+	ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
526
514
 }
527
515
 
528
-static void __init qca956x_clocks_init(void)
516
+static void __init qca956x_clocks_init(void __iomem *pll_base)
529
517
 {
530
518
 	unsigned long ref_rate;
531
519
 	unsigned long cpu_rate;
..
..
@@ -551,13 +539,15 @@
551
539
 	else
552
540
 		ref_rate = 25 * 1000 * 1000;
553
541
 
554
-	pll = ath79_pll_rr(QCA956X_PLL_CPU_CONFIG_REG);
542
+	ref_rate = ath79_setup_ref_clk(ref_rate);
543
+
544
+	pll = __raw_readl(pll_base + QCA956X_PLL_CPU_CONFIG_REG);
555
545
 	out_div = (pll >> QCA956X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
556
546
 		  QCA956X_PLL_CPU_CONFIG_OUTDIV_MASK;
557
547
 	ref_div = (pll >> QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
558
548
 		  QCA956X_PLL_CPU_CONFIG_REFDIV_MASK;
559
549
 
560
-	pll = ath79_pll_rr(QCA956X_PLL_CPU_CONFIG1_REG);
550
+	pll = __raw_readl(pll_base + QCA956X_PLL_CPU_CONFIG1_REG);
561
551
 	nint = (pll >> QCA956X_PLL_CPU_CONFIG1_NINT_SHIFT) &
562
552
 	       QCA956X_PLL_CPU_CONFIG1_NINT_MASK;
563
553
 	hfrac = (pll >> QCA956X_PLL_CPU_CONFIG1_NFRAC_H_SHIFT) &
..
..
@@ -570,12 +560,12 @@
570
560
 	cpu_pll += (hfrac >> 13) * ref_rate / ref_div;
571
561
 	cpu_pll /= (1 << out_div);
572
562
 
573
-	pll = ath79_pll_rr(QCA956X_PLL_DDR_CONFIG_REG);
563
+	pll = __raw_readl(pll_base + QCA956X_PLL_DDR_CONFIG_REG);
574
564
 	out_div = (pll >> QCA956X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
575
565
 		  QCA956X_PLL_DDR_CONFIG_OUTDIV_MASK;
576
566
 	ref_div = (pll >> QCA956X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
577
567
 		  QCA956X_PLL_DDR_CONFIG_REFDIV_MASK;
578
-	pll = ath79_pll_rr(QCA956X_PLL_DDR_CONFIG1_REG);
568
+	pll = __raw_readl(pll_base + QCA956X_PLL_DDR_CONFIG1_REG);
579
569
 	nint = (pll >> QCA956X_PLL_DDR_CONFIG1_NINT_SHIFT) &
580
570
 	       QCA956X_PLL_DDR_CONFIG1_NINT_MASK;
581
571
 	hfrac = (pll >> QCA956X_PLL_DDR_CONFIG1_NFRAC_H_SHIFT) &
..
..
@@ -588,7 +578,7 @@
588
578
 	ddr_pll += (hfrac >> 13) * ref_rate / ref_div;
589
579
 	ddr_pll /= (1 << out_div);
590
580
 
591
-	clk_ctrl = ath79_pll_rr(QCA956X_PLL_CLK_CTRL_REG);
581
+	clk_ctrl = __raw_readl(pll_base + QCA956X_PLL_CLK_CTRL_REG);
592
582
 
593
583
 	postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
594
584
 		  QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
..
..
@@ -620,72 +610,19 @@
620
610
 	else
621
611
 		ahb_rate = cpu_pll / (postdiv + 1);
622
612
 
623
-	ath79_add_sys_clkdev("ref", ref_rate);
624
-	ath79_add_sys_clkdev("cpu", cpu_rate);
625
-	ath79_add_sys_clkdev("ddr", ddr_rate);
626
-	ath79_add_sys_clkdev("ahb", ahb_rate);
627
-
628
-	clk_add_alias("wdt", NULL, "ref", NULL);
629
-	clk_add_alias("uart", NULL, "ref", NULL);
613
+	ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
614
+	ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
615
+	ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
630
616
 }
631
617
 
632
-void __init ath79_clocks_init(void)
633
-{
634
-	if (soc_is_ar71xx())
635
-		ar71xx_clocks_init();
636
-	else if (soc_is_ar724x() || soc_is_ar913x())
637
-		ar724x_clocks_init();
638
-	else if (soc_is_ar933x())
639
-		ar933x_clocks_init();
640
-	else if (soc_is_ar934x())
641
-		ar934x_clocks_init();
642
-	else if (soc_is_qca953x())
643
-		qca953x_clocks_init();
644
-	else if (soc_is_qca955x())
645
-		qca955x_clocks_init();
646
-	else if (soc_is_qca956x() || soc_is_tp9343())
647
-		qca956x_clocks_init();
648
-	else
649
-		BUG();
650
-}
651
-
652
-unsigned long __init
653
-ath79_get_sys_clk_rate(const char *id)
654
-{
655
-	struct clk *clk;
656
-	unsigned long rate;
657
-
658
-	clk = clk_get(NULL, id);
659
-	if (IS_ERR(clk))
660
-		panic("unable to get %s clock, err=%d", id, (int) PTR_ERR(clk));
661
-
662
-	rate = clk_get_rate(clk);
663
-	clk_put(clk);
664
-
665
-	return rate;
666
-}
667
-
668
-#ifdef CONFIG_OF
669
618
 static void __init ath79_clocks_init_dt(struct device_node *np)
670
-{
671
-	of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
672
-}
673
-
674
-CLK_OF_DECLARE(ar7100, "qca,ar7100-pll", ath79_clocks_init_dt);
675
-CLK_OF_DECLARE(ar7240, "qca,ar7240-pll", ath79_clocks_init_dt);
676
-CLK_OF_DECLARE(ar9340, "qca,ar9340-pll", ath79_clocks_init_dt);
677
-CLK_OF_DECLARE(ar9550, "qca,qca9550-pll", ath79_clocks_init_dt);
678
-
679
-static void __init ath79_clocks_init_dt_ng(struct device_node *np)
680
619
 {
681
620
 	struct clk *ref_clk;
682
621
 	void __iomem *pll_base;
683
622
 
684
623
 	ref_clk = of_clk_get(np, 0);
685
-	if (IS_ERR(ref_clk)) {
686
-		pr_err("%pOF: of_clk_get failed\n", np);
687
-		goto err;
688
-	}
624
+	if (!IS_ERR(ref_clk))
625
+		clks[ATH79_CLK_REF] = ref_clk;
689
626
 
690
627
 	pll_base = of_iomap(np, 0);
691
628
 	if (!pll_base) {
..
..
@@ -693,14 +630,24 @@
693
630
 		goto err_clk;
694
631
 	}
695
632
 
696
-	if (of_device_is_compatible(np, "qca,ar9130-pll"))
697
-		ar724x_clk_init(ref_clk, pll_base);
633
+	if (of_device_is_compatible(np, "qca,ar7100-pll"))
634
+		ar71xx_clocks_init(pll_base);
635
+	else if (of_device_is_compatible(np, "qca,ar7240-pll") ||
636
+		 of_device_is_compatible(np, "qca,ar9130-pll"))
637
+		ar724x_clocks_init(pll_base);
698
638
 	else if (of_device_is_compatible(np, "qca,ar9330-pll"))
699
-		ar9330_clk_init(ref_clk, pll_base);
700
-	else {
701
-		pr_err("%pOF: could not find any appropriate clk_init()\n", np);
702
-		goto err_iounmap;
703
-	}
639
+		ar933x_clocks_init(pll_base);
640
+	else if (of_device_is_compatible(np, "qca,ar9340-pll"))
641
+		ar934x_clocks_init(pll_base);
642
+	else if (of_device_is_compatible(np, "qca,qca9530-pll"))
643
+		qca953x_clocks_init(pll_base);
644
+	else if (of_device_is_compatible(np, "qca,qca9550-pll"))
645
+		qca955x_clocks_init(pll_base);
646
+	else if (of_device_is_compatible(np, "qca,qca9560-pll"))
647
+		qca956x_clocks_init(pll_base);
648
+
649
+	if (!clks[ATH79_CLK_MDIO])
650
+		clks[ATH79_CLK_MDIO] = clks[ATH79_CLK_REF];
704
651
 
705
652
 	if (of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data)) {
706
653
 		pr_err("%pOF: could not register clk provider\n", np);
..
..
@@ -714,10 +661,13 @@
714
661
 
715
662
 err_clk:
716
663
 	clk_put(ref_clk);
717
-
718
-err:
719
-	return;
720
664
 }
721
-CLK_OF_DECLARE(ar9130_clk, "qca,ar9130-pll", ath79_clocks_init_dt_ng);
722
-CLK_OF_DECLARE(ar9330_clk, "qca,ar9330-pll", ath79_clocks_init_dt_ng);
723
-#endif
665
+
666
+CLK_OF_DECLARE(ar7100_clk, "qca,ar7100-pll", ath79_clocks_init_dt);
667
+CLK_OF_DECLARE(ar7240_clk, "qca,ar7240-pll", ath79_clocks_init_dt);
668
+CLK_OF_DECLARE(ar9130_clk, "qca,ar9130-pll", ath79_clocks_init_dt);
669
+CLK_OF_DECLARE(ar9330_clk, "qca,ar9330-pll", ath79_clocks_init_dt);
670
+CLK_OF_DECLARE(ar9340_clk, "qca,ar9340-pll", ath79_clocks_init_dt);
671
+CLK_OF_DECLARE(ar9530_clk, "qca,qca9530-pll", ath79_clocks_init_dt);
672
+CLK_OF_DECLARE(ar9550_clk, "qca,qca9550-pll", ath79_clocks_init_dt);
673
+CLK_OF_DECLARE(ar9560_clk, "qca,qca9560-pll", ath79_clocks_init_dt);