add new system file

hc

2024-02-20 102a0743326a03cd1a1202ceda21e175b7d3575c

 kernel/arch/microblaze/mm/consistent.c
..
..
@@ -1,222 +1,52 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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 /*
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  * Microblaze support for cache consistent memory.
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  * Copyright (C) 2010 Michal Simek <monstr@monstr.eu>
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  * Copyright (C) 2010 PetaLogix
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  * Copyright (C) 2005 John Williams <jwilliams@itee.uq.edu.au>
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- *
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- * Based on PowerPC version derived from arch/arm/mm/consistent.c
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- * Copyright (C) 2001 Dan Malek (dmalek@jlc.net)
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- * Copyright (C) 2000 Russell King
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License version 2 as
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- * published by the Free Software Foundation.
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  */
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8
 
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-#include <linux/export.h>
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-#include <linux/signal.h>
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-#include <linux/sched.h>
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 #include <linux/kernel.h>
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-#include <linux/errno.h>
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 #include <linux/string.h>
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 #include <linux/types.h>
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-#include <linux/ptrace.h>
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-#include <linux/mman.h>
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 #include <linux/mm.h>
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-#include <linux/swap.h>
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-#include <linux/stddef.h>
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-#include <linux/vmalloc.h>
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 #include <linux/init.h>
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-#include <linux/delay.h>
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-#include <linux/bootmem.h>
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-#include <linux/highmem.h>
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-#include <linux/pci.h>
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-#include <linux/interrupt.h>
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-#include <linux/gfp.h>
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-#include <linux/dma-noncoherent.h>
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-
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-#include <asm/pgalloc.h>
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-#include <linux/io.h>
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-#include <linux/hardirq.h>
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-#include <linux/mmu_context.h>
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-#include <asm/mmu.h>
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-#include <linux/uaccess.h>
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-#include <asm/pgtable.h>
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+#include <linux/dma-map-ops.h>
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 #include <asm/cpuinfo.h>
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-#include <asm/tlbflush.h>
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+#include <asm/cacheflush.h>
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17
 
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-#ifndef CONFIG_MMU
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-/* I have to use dcache values because I can't relate on ram size */
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-# define UNCACHED_SHADOW_MASK (cpuinfo.dcache_high - cpuinfo.dcache_base + 1)
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-#endif
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-
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-/*
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- * Consistent memory allocators. Used for DMA devices that want to
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- * share uncached memory with the processor core.
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- * My crufty no-MMU approach is simple. In the HW platform we can optionally
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- * mirror the DDR up above the processor cacheable region.  So, memory accessed
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- * in this mirror region will not be cached.  It's alloced from the same
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- * pool as normal memory, but the handle we return is shifted up into the
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- * uncached region.  This will no doubt cause big problems if memory allocated
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- * here is not also freed properly. -- JW
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- */
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-void *arch_dma_alloc(struct device *dev, size_t size, dma_addr_t *dma_handle,
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-		gfp_t gfp, unsigned long attrs)
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+void arch_dma_prep_coherent(struct page *page, size_t size)
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 {
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-	unsigned long order, vaddr;
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-	void *ret;
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-	unsigned int i, err = 0;
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-	struct page *page, *end;
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+	phys_addr_t paddr = page_to_phys(page);
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21
 
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-#ifdef CONFIG_MMU
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-	phys_addr_t pa;
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-	struct vm_struct *area;
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-	unsigned long va;
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-#endif
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-
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-	if (in_interrupt())
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-		BUG();
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-
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-	/* Only allocate page size areas. */
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-	size = PAGE_ALIGN(size);
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-	order = get_order(size);
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-
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-	vaddr = __get_free_pages(gfp, order);
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-	if (!vaddr)
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-		return NULL;
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-
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-	/*
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-	 * we need to ensure that there are no cachelines in use,
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-	 * or worse dirty in this area.
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-	 */
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-	flush_dcache_range(virt_to_phys((void *)vaddr),
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-					virt_to_phys((void *)vaddr) + size);
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+	flush_dcache_range(paddr, paddr + size);
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+}
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 #ifndef CONFIG_MMU
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-	ret = (void *)vaddr;
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-	/*
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-	 * Here's the magic!  Note if the uncached shadow is not implemented,
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-	 * it's up to the calling code to also test that condition and make
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-	 * other arranegments, such as manually flushing the cache and so on.
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-	 */
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-# ifdef CONFIG_XILINX_UNCACHED_SHADOW
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-	ret = (void *)((unsigned) ret | UNCACHED_SHADOW_MASK);
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-# endif
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-	if ((unsigned int)ret > cpuinfo.dcache_base &&
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-				(unsigned int)ret < cpuinfo.dcache_high)
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+/*
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+ * Consistent memory allocators. Used for DMA devices that want to share
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+ * uncached memory with the processor core.  My crufty no-MMU approach is
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+ * simple.  In the HW platform we can optionally mirror the DDR up above the
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+ * processor cacheable region.  So, memory accessed in this mirror region will
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+ * not be cached.  It's alloced from the same pool as normal memory, but the
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+ * handle we return is shifted up into the uncached region.  This will no doubt
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+ * cause big problems if memory allocated here is not also freed properly. -- JW
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+ *
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+ * I have to use dcache values because I can't relate on ram size:
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+ */
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+#ifdef CONFIG_XILINX_UNCACHED_SHADOW
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+#define UNCACHED_SHADOW_MASK (cpuinfo.dcache_high - cpuinfo.dcache_base + 1)
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+#else
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+#define UNCACHED_SHADOW_MASK 0
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+#endif /* CONFIG_XILINX_UNCACHED_SHADOW */
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+
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+void *arch_dma_set_uncached(void *ptr, size_t size)
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+{
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+	unsigned long addr = (unsigned long)ptr;
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+
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+	addr |= UNCACHED_SHADOW_MASK;
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+	if (addr > cpuinfo.dcache_base && addr < cpuinfo.dcache_high)
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 		pr_warn("ERROR: Your cache coherent area is CACHED!!!\n");
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-
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-	/* dma_handle is same as physical (shadowed) address */
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-	*dma_handle = (dma_addr_t)ret;
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-#else
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-	/* Allocate some common virtual space to map the new pages. */
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-	area = get_vm_area(size, VM_ALLOC);
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-	if (!area) {
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-		free_pages(vaddr, order);
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-		return NULL;
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-	}
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-	va = (unsigned long) area->addr;
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-	ret = (void *)va;
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-
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-	/* This gives us the real physical address of the first page. */
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-	*dma_handle = pa = __virt_to_phys(vaddr);
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-#endif
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-
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-	/*
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-	 * free wasted pages.  We skip the first page since we know
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-	 * that it will have count = 1 and won't require freeing.
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-	 * We also mark the pages in use as reserved so that
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-	 * remap_page_range works.
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-	 */
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-	page = virt_to_page(vaddr);
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-	end = page + (1 << order);
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-
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-	split_page(page, order);
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-
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-	for (i = 0; i < size && err == 0; i += PAGE_SIZE) {
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-#ifdef CONFIG_MMU
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-		/* MS: This is the whole magic - use cache inhibit pages */
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-		err = map_page(va + i, pa + i, _PAGE_KERNEL | _PAGE_NO_CACHE);
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-#endif
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-
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-		SetPageReserved(page);
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-		page++;
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-	}
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-
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-	/* Free the otherwise unused pages. */
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-	while (page < end) {
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-		__free_page(page);
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-		page++;
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-	}
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-
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-	if (err) {
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-		free_pages(vaddr, order);
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-		return NULL;
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-	}
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-
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-	return ret;
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+	return (void *)addr;
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 }
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-
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-#ifdef CONFIG_MMU
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-static pte_t *consistent_virt_to_pte(void *vaddr)
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-{
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-	unsigned long addr = (unsigned long)vaddr;
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-
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-	return pte_offset_kernel(pmd_offset(pgd_offset_k(addr), addr), addr);
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-}
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-
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-unsigned long consistent_virt_to_pfn(void *vaddr)
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-{
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-	pte_t *ptep = consistent_virt_to_pte(vaddr);
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-
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-	if (pte_none(*ptep) || !pte_present(*ptep))
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-		return 0;
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-
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-	return pte_pfn(*ptep);
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-}
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-#endif
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-
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-/*
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- * free page(s) as defined by the above mapping.
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- */
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-void arch_dma_free(struct device *dev, size_t size, void *vaddr,
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-		dma_addr_t dma_addr, unsigned long attrs)
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-{
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-	struct page *page;
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-
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-	if (in_interrupt())
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-		BUG();
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-
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-	size = PAGE_ALIGN(size);
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-
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-#ifndef CONFIG_MMU
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-	/* Clear SHADOW_MASK bit in address, and free as per usual */
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-# ifdef CONFIG_XILINX_UNCACHED_SHADOW
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-	vaddr = (void *)((unsigned)vaddr & ~UNCACHED_SHADOW_MASK);
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-# endif
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-	page = virt_to_page(vaddr);
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-
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-	do {
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-		__free_reserved_page(page);
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-		page++;
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-	} while (size -= PAGE_SIZE);
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-#else
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-	do {
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-		pte_t *ptep = consistent_virt_to_pte(vaddr);
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-		unsigned long pfn;
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-
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-		if (!pte_none(*ptep) && pte_present(*ptep)) {
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-			pfn = pte_pfn(*ptep);
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-			pte_clear(&init_mm, (unsigned int)vaddr, ptep);
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-			if (pfn_valid(pfn)) {
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-				page = pfn_to_page(pfn);
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-				__free_reserved_page(page);
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-			}
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-		}
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-		vaddr += PAGE_SIZE;
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-	} while (size -= PAGE_SIZE);
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-
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-	/* flush tlb */
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-	flush_tlb_all();
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-#endif
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-}
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+#endif /* CONFIG_MMU */