.. | .. |
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| 1 | +// SPDX-License-Identifier: GPL-2.0-only |
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1 | 2 | /* |
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2 | 3 | * Copyright (C) 2014-2017 Linaro Ltd. <ard.biesheuvel@linaro.org> |
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3 | | - * |
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4 | | - * This program is free software; you can redistribute it and/or modify |
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5 | | - * it under the terms of the GNU General Public License version 2 as |
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6 | | - * published by the Free Software Foundation. |
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7 | 4 | */ |
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8 | 5 | |
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9 | 6 | #include <linux/elf.h> |
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| 7 | +#include <linux/ftrace.h> |
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10 | 8 | #include <linux/kernel.h> |
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11 | 9 | #include <linux/module.h> |
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| 10 | +#include <linux/moduleloader.h> |
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| 11 | +#include <linux/slab.h> |
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12 | 12 | #include <linux/sort.h> |
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| 13 | + |
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| 14 | +static struct plt_entry __get_adrp_add_pair(u64 dst, u64 pc, |
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| 15 | + enum aarch64_insn_register reg) |
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| 16 | +{ |
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| 17 | + u32 adrp, add; |
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| 18 | + |
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| 19 | + adrp = aarch64_insn_gen_adr(pc, dst, reg, AARCH64_INSN_ADR_TYPE_ADRP); |
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| 20 | + add = aarch64_insn_gen_add_sub_imm(reg, reg, dst % SZ_4K, |
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| 21 | + AARCH64_INSN_VARIANT_64BIT, |
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| 22 | + AARCH64_INSN_ADSB_ADD); |
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| 23 | + |
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| 24 | + return (struct plt_entry){ cpu_to_le32(adrp), cpu_to_le32(add) }; |
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| 25 | +} |
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| 26 | + |
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| 27 | +struct plt_entry get_plt_entry(u64 dst, void *pc) |
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| 28 | +{ |
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| 29 | + struct plt_entry plt; |
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| 30 | + static u32 br; |
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| 31 | + |
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| 32 | + if (!br) |
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| 33 | + br = aarch64_insn_gen_branch_reg(AARCH64_INSN_REG_16, |
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| 34 | + AARCH64_INSN_BRANCH_NOLINK); |
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| 35 | + |
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| 36 | + plt = __get_adrp_add_pair(dst, (u64)pc, AARCH64_INSN_REG_16); |
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| 37 | + plt.br = cpu_to_le32(br); |
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| 38 | + |
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| 39 | + return plt; |
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| 40 | +} |
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| 41 | + |
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| 42 | +bool plt_entries_equal(const struct plt_entry *a, const struct plt_entry *b) |
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| 43 | +{ |
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| 44 | + u64 p, q; |
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| 45 | + |
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| 46 | + /* |
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| 47 | + * Check whether both entries refer to the same target: |
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| 48 | + * do the cheapest checks first. |
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| 49 | + * If the 'add' or 'br' opcodes are different, then the target |
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| 50 | + * cannot be the same. |
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| 51 | + */ |
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| 52 | + if (a->add != b->add || a->br != b->br) |
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| 53 | + return false; |
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| 54 | + |
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| 55 | + p = ALIGN_DOWN((u64)a, SZ_4K); |
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| 56 | + q = ALIGN_DOWN((u64)b, SZ_4K); |
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| 57 | + |
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| 58 | + /* |
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| 59 | + * If the 'adrp' opcodes are the same then we just need to check |
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| 60 | + * that they refer to the same 4k region. |
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| 61 | + */ |
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| 62 | + if (a->adrp == b->adrp && p == q) |
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| 63 | + return true; |
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| 64 | + |
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| 65 | + return (p + aarch64_insn_adrp_get_offset(le32_to_cpu(a->adrp))) == |
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| 66 | + (q + aarch64_insn_adrp_get_offset(le32_to_cpu(b->adrp))); |
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| 67 | +} |
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13 | 68 | |
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14 | 69 | static bool in_init(const struct module *mod, void *loc) |
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15 | 70 | { |
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16 | 71 | return (u64)loc - (u64)mod->init_layout.base < mod->init_layout.size; |
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17 | 72 | } |
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18 | 73 | |
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19 | | -u64 module_emit_plt_entry(struct module *mod, void *loc, const Elf64_Rela *rela, |
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| 74 | +u64 module_emit_plt_entry(struct module *mod, Elf64_Shdr *sechdrs, |
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| 75 | + void *loc, const Elf64_Rela *rela, |
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20 | 76 | Elf64_Sym *sym) |
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21 | 77 | { |
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22 | 78 | struct mod_plt_sec *pltsec = !in_init(mod, loc) ? &mod->arch.core : |
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23 | 79 | &mod->arch.init; |
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24 | | - struct plt_entry *plt = (struct plt_entry *)pltsec->plt->sh_addr; |
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| 80 | + struct plt_entry *plt = (struct plt_entry *)sechdrs[pltsec->plt_shndx].sh_addr; |
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25 | 81 | int i = pltsec->plt_num_entries; |
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| 82 | + int j = i - 1; |
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26 | 83 | u64 val = sym->st_value + rela->r_addend; |
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27 | 84 | |
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28 | | - plt[i] = get_plt_entry(val); |
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| 85 | + if (is_forbidden_offset_for_adrp(&plt[i].adrp)) |
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| 86 | + i++; |
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| 87 | + |
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| 88 | + plt[i] = get_plt_entry(val, &plt[i]); |
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29 | 89 | |
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30 | 90 | /* |
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31 | 91 | * Check if the entry we just created is a duplicate. Given that the |
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32 | 92 | * relocations are sorted, this will be the last entry we allocated. |
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33 | 93 | * (if one exists). |
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34 | 94 | */ |
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35 | | - if (i > 0 && plt_entries_equal(plt + i, plt + i - 1)) |
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36 | | - return (u64)&plt[i - 1]; |
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| 95 | + if (j >= 0 && plt_entries_equal(plt + i, plt + j)) |
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| 96 | + return (u64)&plt[j]; |
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37 | 97 | |
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38 | | - pltsec->plt_num_entries++; |
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| 98 | + pltsec->plt_num_entries += i - j; |
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39 | 99 | if (WARN_ON(pltsec->plt_num_entries > pltsec->plt_max_entries)) |
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40 | 100 | return 0; |
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41 | 101 | |
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.. | .. |
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43 | 103 | } |
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44 | 104 | |
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45 | 105 | #ifdef CONFIG_ARM64_ERRATUM_843419 |
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46 | | -u64 module_emit_veneer_for_adrp(struct module *mod, void *loc, u64 val) |
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| 106 | +u64 module_emit_veneer_for_adrp(struct module *mod, Elf64_Shdr *sechdrs, |
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| 107 | + void *loc, u64 val) |
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47 | 108 | { |
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48 | 109 | struct mod_plt_sec *pltsec = !in_init(mod, loc) ? &mod->arch.core : |
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49 | 110 | &mod->arch.init; |
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50 | | - struct plt_entry *plt = (struct plt_entry *)pltsec->plt->sh_addr; |
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| 111 | + struct plt_entry *plt = (struct plt_entry *)sechdrs[pltsec->plt_shndx].sh_addr; |
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51 | 112 | int i = pltsec->plt_num_entries++; |
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52 | | - u32 mov0, mov1, mov2, br; |
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| 113 | + u32 br; |
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53 | 114 | int rd; |
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54 | 115 | |
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55 | 116 | if (WARN_ON(pltsec->plt_num_entries > pltsec->plt_max_entries)) |
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56 | 117 | return 0; |
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57 | 118 | |
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| 119 | + if (is_forbidden_offset_for_adrp(&plt[i].adrp)) |
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| 120 | + i = pltsec->plt_num_entries++; |
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| 121 | + |
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58 | 122 | /* get the destination register of the ADRP instruction */ |
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59 | 123 | rd = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RD, |
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60 | 124 | le32_to_cpup((__le32 *)loc)); |
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61 | 125 | |
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62 | | - /* generate the veneer instructions */ |
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63 | | - mov0 = aarch64_insn_gen_movewide(rd, (u16)~val, 0, |
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64 | | - AARCH64_INSN_VARIANT_64BIT, |
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65 | | - AARCH64_INSN_MOVEWIDE_INVERSE); |
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66 | | - mov1 = aarch64_insn_gen_movewide(rd, (u16)(val >> 16), 16, |
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67 | | - AARCH64_INSN_VARIANT_64BIT, |
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68 | | - AARCH64_INSN_MOVEWIDE_KEEP); |
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69 | | - mov2 = aarch64_insn_gen_movewide(rd, (u16)(val >> 32), 32, |
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70 | | - AARCH64_INSN_VARIANT_64BIT, |
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71 | | - AARCH64_INSN_MOVEWIDE_KEEP); |
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72 | 126 | br = aarch64_insn_gen_branch_imm((u64)&plt[i].br, (u64)loc + 4, |
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73 | 127 | AARCH64_INSN_BRANCH_NOLINK); |
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74 | 128 | |
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75 | | - plt[i] = (struct plt_entry){ |
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76 | | - cpu_to_le32(mov0), |
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77 | | - cpu_to_le32(mov1), |
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78 | | - cpu_to_le32(mov2), |
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79 | | - cpu_to_le32(br) |
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80 | | - }; |
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| 129 | + plt[i] = __get_adrp_add_pair(val, (u64)&plt[i], rd); |
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| 130 | + plt[i].br = cpu_to_le32(br); |
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81 | 131 | |
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82 | 132 | return (u64)&plt[i]; |
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83 | 133 | } |
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.. | .. |
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193 | 243 | break; |
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194 | 244 | } |
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195 | 245 | } |
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| 246 | + |
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| 247 | + if (IS_ENABLED(CONFIG_ARM64_ERRATUM_843419) && |
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| 248 | + cpus_have_const_cap(ARM64_WORKAROUND_843419)) |
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| 249 | + /* |
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| 250 | + * Add some slack so we can skip PLT slots that may trigger |
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| 251 | + * the erratum due to the placement of the ADRP instruction. |
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| 252 | + */ |
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| 253 | + ret += DIV_ROUND_UP(ret, (SZ_4K / sizeof(struct plt_entry))); |
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| 254 | + |
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196 | 255 | return ret; |
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| 256 | +} |
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| 257 | + |
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| 258 | +static bool branch_rela_needs_plt(Elf64_Sym *syms, Elf64_Rela *rela, |
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| 259 | + Elf64_Word dstidx) |
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| 260 | +{ |
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| 261 | + |
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| 262 | + Elf64_Sym *s = syms + ELF64_R_SYM(rela->r_info); |
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| 263 | + |
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| 264 | + if (s->st_shndx == dstidx) |
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| 265 | + return false; |
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| 266 | + |
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| 267 | + return ELF64_R_TYPE(rela->r_info) == R_AARCH64_JUMP26 || |
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| 268 | + ELF64_R_TYPE(rela->r_info) == R_AARCH64_CALL26; |
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| 269 | +} |
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| 270 | + |
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| 271 | +/* Group branch PLT relas at the front end of the array. */ |
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| 272 | +static int partition_branch_plt_relas(Elf64_Sym *syms, Elf64_Rela *rela, |
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| 273 | + int numrels, Elf64_Word dstidx) |
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| 274 | +{ |
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| 275 | + int i = 0, j = numrels - 1; |
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| 276 | + |
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| 277 | + if (!IS_ENABLED(CONFIG_RANDOMIZE_BASE)) |
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| 278 | + return 0; |
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| 279 | + |
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| 280 | + while (i < j) { |
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| 281 | + if (branch_rela_needs_plt(syms, &rela[i], dstidx)) |
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| 282 | + i++; |
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| 283 | + else if (branch_rela_needs_plt(syms, &rela[j], dstidx)) |
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| 284 | + swap(rela[i], rela[j]); |
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| 285 | + else |
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| 286 | + j--; |
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| 287 | + } |
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| 288 | + |
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| 289 | + return i; |
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197 | 290 | } |
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198 | 291 | |
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199 | 292 | int module_frob_arch_sections(Elf_Ehdr *ehdr, Elf_Shdr *sechdrs, |
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200 | 293 | char *secstrings, struct module *mod) |
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201 | 294 | { |
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| 295 | + bool copy_rela_for_fips140 = false; |
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202 | 296 | unsigned long core_plts = 0; |
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203 | 297 | unsigned long init_plts = 0; |
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204 | 298 | Elf64_Sym *syms = NULL; |
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205 | | - Elf_Shdr *tramp = NULL; |
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| 299 | + Elf_Shdr *pltsec, *tramp = NULL; |
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206 | 300 | int i; |
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207 | 301 | |
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208 | 302 | /* |
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.. | .. |
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211 | 305 | */ |
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212 | 306 | for (i = 0; i < ehdr->e_shnum; i++) { |
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213 | 307 | if (!strcmp(secstrings + sechdrs[i].sh_name, ".plt")) |
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214 | | - mod->arch.core.plt = sechdrs + i; |
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| 308 | + mod->arch.core.plt_shndx = i; |
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215 | 309 | else if (!strcmp(secstrings + sechdrs[i].sh_name, ".init.plt")) |
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216 | | - mod->arch.init.plt = sechdrs + i; |
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217 | | - else if (IS_ENABLED(CONFIG_DYNAMIC_FTRACE) && |
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218 | | - !strcmp(secstrings + sechdrs[i].sh_name, |
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| 310 | + mod->arch.init.plt_shndx = i; |
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| 311 | + else if (!strcmp(secstrings + sechdrs[i].sh_name, |
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219 | 312 | ".text.ftrace_trampoline")) |
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220 | 313 | tramp = sechdrs + i; |
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221 | 314 | else if (sechdrs[i].sh_type == SHT_SYMTAB) |
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222 | 315 | syms = (Elf64_Sym *)sechdrs[i].sh_addr; |
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223 | 316 | } |
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224 | 317 | |
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225 | | - if (!mod->arch.core.plt || !mod->arch.init.plt) { |
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| 318 | + if (!mod->arch.core.plt_shndx || !mod->arch.init.plt_shndx) { |
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226 | 319 | pr_err("%s: module PLT section(s) missing\n", mod->name); |
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227 | 320 | return -ENOEXEC; |
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228 | 321 | } |
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.. | .. |
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231 | 324 | return -ENOEXEC; |
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232 | 325 | } |
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233 | 326 | |
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| 327 | + if (IS_ENABLED(CONFIG_CRYPTO_FIPS140) && |
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| 328 | + !strcmp(mod->name, "fips140")) |
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| 329 | + copy_rela_for_fips140 = true; |
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| 330 | + |
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234 | 331 | for (i = 0; i < ehdr->e_shnum; i++) { |
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235 | 332 | Elf64_Rela *rels = (void *)ehdr + sechdrs[i].sh_offset; |
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236 | | - int numrels = sechdrs[i].sh_size / sizeof(Elf64_Rela); |
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| 333 | + int nents, numrels = sechdrs[i].sh_size / sizeof(Elf64_Rela); |
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237 | 334 | Elf64_Shdr *dstsec = sechdrs + sechdrs[i].sh_info; |
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238 | 335 | |
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239 | 336 | if (sechdrs[i].sh_type != SHT_RELA) |
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240 | 337 | continue; |
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241 | 338 | |
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| 339 | +#ifdef CONFIG_CRYPTO_FIPS140 |
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| 340 | + if (copy_rela_for_fips140 && |
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| 341 | + !strcmp(secstrings + dstsec->sh_name, ".rodata")) { |
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| 342 | + void *p = kmemdup(rels, numrels * sizeof(Elf64_Rela), |
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| 343 | + GFP_KERNEL); |
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| 344 | + if (!p) { |
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| 345 | + pr_err("fips140: failed to allocate .rodata RELA buffer\n"); |
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| 346 | + return -ENOMEM; |
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| 347 | + } |
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| 348 | + mod->arch.rodata_relocations = p; |
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| 349 | + mod->arch.num_rodata_relocations = numrels; |
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| 350 | + } |
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| 351 | +#endif |
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| 352 | + |
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242 | 353 | /* ignore relocations that operate on non-exec sections */ |
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243 | 354 | if (!(dstsec->sh_flags & SHF_EXECINSTR)) |
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244 | 355 | continue; |
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245 | 356 | |
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246 | | - /* sort by type, symbol index and addend */ |
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247 | | - sort(rels, numrels, sizeof(Elf64_Rela), cmp_rela, NULL); |
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| 357 | +#ifdef CONFIG_CRYPTO_FIPS140 |
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| 358 | + if (copy_rela_for_fips140 && |
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| 359 | + !strcmp(secstrings + dstsec->sh_name, ".text")) { |
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| 360 | + void *p = kmemdup(rels, numrels * sizeof(Elf64_Rela), |
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| 361 | + GFP_KERNEL); |
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| 362 | + if (!p) { |
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| 363 | + pr_err("fips140: failed to allocate .text RELA buffer\n"); |
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| 364 | + return -ENOMEM; |
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| 365 | + } |
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| 366 | + mod->arch.text_relocations = p; |
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| 367 | + mod->arch.num_text_relocations = numrels; |
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| 368 | + } |
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| 369 | +#endif |
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248 | 370 | |
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249 | | - if (strncmp(secstrings + dstsec->sh_name, ".init", 5) != 0) |
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| 371 | + /* |
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| 372 | + * sort branch relocations requiring a PLT by type, symbol index |
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| 373 | + * and addend |
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| 374 | + */ |
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| 375 | + nents = partition_branch_plt_relas(syms, rels, numrels, |
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| 376 | + sechdrs[i].sh_info); |
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| 377 | + if (nents) |
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| 378 | + sort(rels, nents, sizeof(Elf64_Rela), cmp_rela, NULL); |
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| 379 | + |
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| 380 | + if (!module_init_layout_section(secstrings + dstsec->sh_name)) |
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250 | 381 | core_plts += count_plts(syms, rels, numrels, |
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251 | 382 | sechdrs[i].sh_info, dstsec); |
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252 | 383 | else |
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.. | .. |
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254 | 385 | sechdrs[i].sh_info, dstsec); |
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255 | 386 | } |
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256 | 387 | |
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257 | | - mod->arch.core.plt->sh_type = SHT_NOBITS; |
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258 | | - mod->arch.core.plt->sh_flags = SHF_EXECINSTR | SHF_ALLOC; |
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259 | | - mod->arch.core.plt->sh_addralign = L1_CACHE_BYTES; |
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260 | | - mod->arch.core.plt->sh_size = (core_plts + 1) * sizeof(struct plt_entry); |
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| 388 | + pltsec = sechdrs + mod->arch.core.plt_shndx; |
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| 389 | + pltsec->sh_type = SHT_NOBITS; |
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| 390 | + pltsec->sh_flags = SHF_EXECINSTR | SHF_ALLOC; |
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| 391 | + pltsec->sh_addralign = L1_CACHE_BYTES; |
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| 392 | + pltsec->sh_size = (core_plts + 1) * sizeof(struct plt_entry); |
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261 | 393 | mod->arch.core.plt_num_entries = 0; |
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262 | 394 | mod->arch.core.plt_max_entries = core_plts; |
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263 | 395 | |
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264 | | - mod->arch.init.plt->sh_type = SHT_NOBITS; |
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265 | | - mod->arch.init.plt->sh_flags = SHF_EXECINSTR | SHF_ALLOC; |
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266 | | - mod->arch.init.plt->sh_addralign = L1_CACHE_BYTES; |
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267 | | - mod->arch.init.plt->sh_size = (init_plts + 1) * sizeof(struct plt_entry); |
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| 396 | + pltsec = sechdrs + mod->arch.init.plt_shndx; |
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| 397 | + pltsec->sh_type = SHT_NOBITS; |
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| 398 | + pltsec->sh_flags = SHF_EXECINSTR | SHF_ALLOC; |
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| 399 | + pltsec->sh_addralign = L1_CACHE_BYTES; |
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| 400 | + pltsec->sh_size = (init_plts + 1) * sizeof(struct plt_entry); |
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268 | 401 | mod->arch.init.plt_num_entries = 0; |
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269 | 402 | mod->arch.init.plt_max_entries = init_plts; |
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270 | 403 | |
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.. | .. |
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272 | 405 | tramp->sh_type = SHT_NOBITS; |
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273 | 406 | tramp->sh_flags = SHF_EXECINSTR | SHF_ALLOC; |
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274 | 407 | tramp->sh_addralign = __alignof__(struct plt_entry); |
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275 | | - tramp->sh_size = sizeof(struct plt_entry); |
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| 408 | + tramp->sh_size = NR_FTRACE_PLTS * sizeof(struct plt_entry); |
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276 | 409 | } |
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277 | 410 | |
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278 | 411 | return 0; |
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