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2024-02-20 102a0743326a03cd1a1202ceda21e175b7d3575c

 kernel/arch/arm/mach-omap2/omap_hwmod_81xx_data.c
..
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@@ -1,7 +1,7 @@
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 /*
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  * DM81xx hwmod data.
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  *
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- * Copyright (C) 2010 Texas Instruments, Inc. - http://www.ti.com/
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+ * Copyright (C) 2010 Texas Instruments, Inc. - https://www.ti.com/
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  * Copyright (C) 2013 SKTB SKiT, http://www.skitlab.ru/
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  *
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  * This program is free software; you can redistribute it and/or
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@@ -125,13 +125,6 @@
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 static struct omap_hwmod dm81xx_alwon_l3_med_hwmod = {
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 	.name		= "l3_med",
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 	.clkdm_name	= "alwon_l3_med_clkdm",
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-	.class		= &l3_hwmod_class,
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-	.flags		= HWMOD_NO_IDLEST,
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-};
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-
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-static struct omap_hwmod dm81xx_alwon_l3_fast_hwmod = {
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-	.name		= "l3_fast",
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-	.clkdm_name	= "alwon_l3_fast_clkdm",
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 	.class		= &l3_hwmod_class,
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 	.flags		= HWMOD_NO_IDLEST,
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 };
..
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@@ -432,6 +425,13 @@
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 	.class		= &i2c_class,
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 };
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+static struct omap_hwmod_ocp_if dm81xx_l4_ls__i2c2 = {
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+	.master		= &dm81xx_l4_ls_hwmod,
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+	.slave		= &dm81xx_i2c2_hwmod,
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+	.clk		= "sysclk6_ck",
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+	.user		= OCP_USER_MPU,
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+};
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+
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 static struct omap_hwmod_class_sysconfig dm81xx_elm_sysc = {
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 	.rev_offs	= 0x0000,
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 	.sysc_offs	= 0x0010,
..
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@@ -441,13 +441,6 @@
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 				SYSS_HAS_RESET_STATUS,
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 	.idlemodes	= SIDLE_FORCE | SIDLE_NO | SIDLE_SMART,
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 	.sysc_fields	= &omap_hwmod_sysc_type1,
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-};
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-
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-static struct omap_hwmod_ocp_if dm81xx_l4_ls__i2c2 = {
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-	.master		= &dm81xx_l4_ls_hwmod,
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-	.slave		= &dm81xx_i2c2_hwmod,
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-	.clk		= "sysclk6_ck",
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-	.user		= OCP_USER_MPU,
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 };
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 static struct omap_hwmod_class dm81xx_elm_hwmod_class = {
..
..
@@ -484,7 +477,6 @@
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 static struct omap_hwmod_class dm81xx_gpio_hwmod_class = {
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 	.name	= "gpio",
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 	.sysc	= &dm81xx_gpio_sysc,
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-	.rev	= 2,
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 };
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 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
..
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@@ -535,6 +527,58 @@
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 static struct omap_hwmod_ocp_if dm81xx_l4_ls__gpio2 = {
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 	.master		= &dm81xx_l4_ls_hwmod,
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 	.slave		= &dm81xx_gpio2_hwmod,
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+	.clk		= "sysclk6_ck",
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+	.user		= OCP_USER_MPU,
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+};
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+
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+static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
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+	{ .role = "dbclk", .clk = "sysclk18_ck" },
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+};
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+
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+static struct omap_hwmod dm81xx_gpio3_hwmod = {
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+	.name		= "gpio3",
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+	.clkdm_name	= "alwon_l3s_clkdm",
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+	.class		= &dm81xx_gpio_hwmod_class,
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+	.main_clk	= "sysclk6_ck",
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+	.prcm = {
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+		.omap4 = {
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+			.clkctrl_offs = DM81XX_CM_ALWON_GPIO_1_CLKCTRL,
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+			.modulemode = MODULEMODE_SWCTRL,
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+		},
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+	},
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+	.opt_clks	= gpio3_opt_clks,
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+	.opt_clks_cnt	= ARRAY_SIZE(gpio3_opt_clks),
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+};
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+
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+static struct omap_hwmod_ocp_if dm81xx_l4_ls__gpio3 = {
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+	.master		= &dm81xx_l4_ls_hwmod,
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+	.slave		= &dm81xx_gpio3_hwmod,
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+	.clk		= "sysclk6_ck",
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+	.user		= OCP_USER_MPU,
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+};
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+
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+static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
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+	{ .role = "dbclk", .clk = "sysclk18_ck" },
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+};
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+
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+static struct omap_hwmod dm81xx_gpio4_hwmod = {
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+	.name		= "gpio4",
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+	.clkdm_name	= "alwon_l3s_clkdm",
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+	.class		= &dm81xx_gpio_hwmod_class,
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+	.main_clk	= "sysclk6_ck",
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+	.prcm = {
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+		.omap4 = {
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+			.clkctrl_offs = DM81XX_CM_ALWON_GPIO_1_CLKCTRL,
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+			.modulemode = MODULEMODE_SWCTRL,
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+		},
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+	},
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+	.opt_clks	= gpio4_opt_clks,
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+	.opt_clks_cnt	= ARRAY_SIZE(gpio4_opt_clks),
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+};
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+
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+static struct omap_hwmod_ocp_if dm81xx_l4_ls__gpio4 = {
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+	.master		= &dm81xx_l4_ls_hwmod,
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+	.slave		= &dm81xx_gpio4_hwmod,
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 	.clk		= "sysclk6_ck",
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 	.user		= OCP_USER_MPU,
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 };
..
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@@ -646,76 +690,6 @@
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 	.sysc = &dm816x_timer_sysc,
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 };
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649
-static struct omap_hwmod dm814x_timer1_hwmod = {
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-	.name		= "timer1",
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-	.clkdm_name	= "alwon_l3s_clkdm",
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-	.main_clk	= "timer1_fck",
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-	.class		= &dm816x_timer_hwmod_class,
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-	.flags		= HWMOD_NO_IDLEST,
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-};
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-
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-static struct omap_hwmod_ocp_if dm814x_l4_ls__timer1 = {
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-	.master		= &dm81xx_l4_ls_hwmod,
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-	.slave		= &dm814x_timer1_hwmod,
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-	.clk		= "sysclk6_ck",
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-	.user		= OCP_USER_MPU,
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-};
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-
664
-static struct omap_hwmod dm816x_timer1_hwmod = {
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-	.name		= "timer1",
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-	.clkdm_name	= "alwon_l3s_clkdm",
667
-	.main_clk	= "timer1_fck",
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-	.prcm		= {
669
-		.omap4 = {
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-			.clkctrl_offs = DM816X_CM_ALWON_TIMER_1_CLKCTRL,
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-			.modulemode = MODULEMODE_SWCTRL,
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-		},
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-	},
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-	.class		= &dm816x_timer_hwmod_class,
675
-};
676
-
677
-static struct omap_hwmod_ocp_if dm816x_l4_ls__timer1 = {
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-	.master		= &dm81xx_l4_ls_hwmod,
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-	.slave		= &dm816x_timer1_hwmod,
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-	.clk		= "sysclk6_ck",
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-	.user		= OCP_USER_MPU,
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-};
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-
684
-static struct omap_hwmod dm814x_timer2_hwmod = {
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-	.name		= "timer2",
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-	.clkdm_name	= "alwon_l3s_clkdm",
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-	.main_clk	= "timer2_fck",
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-	.class		= &dm816x_timer_hwmod_class,
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-	.flags		= HWMOD_NO_IDLEST,
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-};
691
-
692
-static struct omap_hwmod_ocp_if dm814x_l4_ls__timer2 = {
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-	.master		= &dm81xx_l4_ls_hwmod,
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-	.slave		= &dm814x_timer2_hwmod,
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-	.clk		= "sysclk6_ck",
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-	.user		= OCP_USER_MPU,
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-};
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-
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-static struct omap_hwmod dm816x_timer2_hwmod = {
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-	.name		= "timer2",
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-	.clkdm_name	= "alwon_l3s_clkdm",
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-	.main_clk	= "timer2_fck",
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-	.prcm		= {
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-		.omap4 = {
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-			.clkctrl_offs = DM816X_CM_ALWON_TIMER_2_CLKCTRL,
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-			.modulemode = MODULEMODE_SWCTRL,
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-		},
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-	},
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-	.class		= &dm816x_timer_hwmod_class,
710
-};
711
-
712
-static struct omap_hwmod_ocp_if dm816x_l4_ls__timer2 = {
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-	.master		= &dm81xx_l4_ls_hwmod,
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-	.slave		= &dm816x_timer2_hwmod,
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-	.clk		= "sysclk6_ck",
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-	.user		= OCP_USER_MPU,
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-};
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-
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 static struct omap_hwmod dm816x_timer3_hwmod = {
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 	.name		= "timer3",
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 	.clkdm_name	= "alwon_l3s_clkdm",
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@@ -814,62 +788,6 @@
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 	.slave		= &dm816x_timer7_hwmod,
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 	.clk		= "sysclk6_ck",
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 	.user		= OCP_USER_MPU,
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-};
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-
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-/* CPSW on dm814x */
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-static struct omap_hwmod_class_sysconfig dm814x_cpgmac_sysc = {
821
-	.rev_offs	= 0x0,
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-	.sysc_offs	= 0x8,
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-	.syss_offs	= 0x4,
824
-	.sysc_flags	= SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
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-			  SYSS_HAS_RESET_STATUS,
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-	.idlemodes	= SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
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-			  MSTANDBY_NO,
828
-	.sysc_fields	= &omap_hwmod_sysc_type3,
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-};
830
-
831
-static struct omap_hwmod_class dm814x_cpgmac0_hwmod_class = {
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-	.name		= "cpgmac0",
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-	.sysc		= &dm814x_cpgmac_sysc,
834
-};
835
-
836
-static struct omap_hwmod dm814x_cpgmac0_hwmod = {
837
-	.name		= "cpgmac0",
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-	.class		= &dm814x_cpgmac0_hwmod_class,
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-	.clkdm_name	= "alwon_ethernet_clkdm",
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-	.flags		= HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
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-	.main_clk	= "cpsw_125mhz_gclk",
842
-	.prcm		= {
843
-		.omap4	= {
844
-			.clkctrl_offs = DM81XX_CM_ALWON_ETHERNET_0_CLKCTRL,
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-			.modulemode = MODULEMODE_SWCTRL,
846
-		},
847
-	},
848
-};
849
-
850
-static struct omap_hwmod_class dm814x_mdio_hwmod_class = {
851
-	.name		= "davinci_mdio",
852
-};
853
-
854
-static struct omap_hwmod dm814x_mdio_hwmod = {
855
-	.name		= "davinci_mdio",
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-	.class		= &dm814x_mdio_hwmod_class,
857
-	.clkdm_name	= "alwon_ethernet_clkdm",
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-	.main_clk	= "cpsw_125mhz_gclk",
859
-};
860
-
861
-static struct omap_hwmod_ocp_if dm814x_l4_hs__cpgmac0 = {
862
-	.master		= &dm81xx_l4_hs_hwmod,
863
-	.slave		= &dm814x_cpgmac0_hwmod,
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-	.clk		= "cpsw_125mhz_gclk",
865
-	.user		= OCP_USER_MPU,
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-};
867
-
868
-static struct omap_hwmod_ocp_if dm814x_cpgmac0__mdio = {
869
-	.master		= &dm814x_cpgmac0_hwmod,
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-	.slave		= &dm814x_mdio_hwmod,
871
-	.user		= OCP_USER_MPU,
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-	.flags		= HWMOD_NO_IDLEST,
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 };
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 /* EMAC Ethernet */
..
..
@@ -1133,9 +1051,69 @@
1133
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 	.class		= &dm816x_mcspi_class,
1134
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 };
1135
1053
 
1054
+static struct omap_hwmod dm81xx_mcspi2_hwmod = {
1055
+	.name		= "mcspi2",
1056
+	.clkdm_name	= "alwon_l3s_clkdm",
1057
+	.main_clk	= "sysclk10_ck",
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+	.prcm		= {
1059
+		.omap4 = {
1060
+			.clkctrl_offs = DM81XX_CM_ALWON_SPI_CLKCTRL,
1061
+			.modulemode = MODULEMODE_SWCTRL,
1062
+		},
1063
+	},
1064
+	.class		= &dm816x_mcspi_class,
1065
+};
1066
+
1067
+static struct omap_hwmod dm81xx_mcspi3_hwmod = {
1068
+	.name		= "mcspi3",
1069
+	.clkdm_name	= "alwon_l3s_clkdm",
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+	.main_clk	= "sysclk10_ck",
1071
+	.prcm		= {
1072
+		.omap4 = {
1073
+			.clkctrl_offs = DM81XX_CM_ALWON_SPI_CLKCTRL,
1074
+			.modulemode = MODULEMODE_SWCTRL,
1075
+		},
1076
+	},
1077
+	.class		= &dm816x_mcspi_class,
1078
+};
1079
+
1080
+static struct omap_hwmod dm81xx_mcspi4_hwmod = {
1081
+	.name		= "mcspi4",
1082
+	.clkdm_name	= "alwon_l3s_clkdm",
1083
+	.main_clk	= "sysclk10_ck",
1084
+	.prcm		= {
1085
+		.omap4 = {
1086
+			.clkctrl_offs = DM81XX_CM_ALWON_SPI_CLKCTRL,
1087
+			.modulemode = MODULEMODE_SWCTRL,
1088
+		},
1089
+	},
1090
+	.class		= &dm816x_mcspi_class,
1091
+};
1092
+
1136
1093
 static struct omap_hwmod_ocp_if dm81xx_l4_ls__mcspi1 = {
1137
1094
 	.master		= &dm81xx_l4_ls_hwmod,
1138
1095
 	.slave		= &dm81xx_mcspi1_hwmod,
1096
+	.clk		= "sysclk6_ck",
1097
+	.user		= OCP_USER_MPU,
1098
+};
1099
+
1100
+static struct omap_hwmod_ocp_if dm81xx_l4_ls__mcspi2 = {
1101
+	.master		= &dm81xx_l4_ls_hwmod,
1102
+	.slave		= &dm81xx_mcspi2_hwmod,
1103
+	.clk		= "sysclk6_ck",
1104
+	.user		= OCP_USER_MPU,
1105
+};
1106
+
1107
+static struct omap_hwmod_ocp_if dm81xx_l4_ls__mcspi3 = {
1108
+	.master		= &dm81xx_l4_ls_hwmod,
1109
+	.slave		= &dm81xx_mcspi3_hwmod,
1110
+	.clk		= "sysclk6_ck",
1111
+	.user		= OCP_USER_MPU,
1112
+};
1113
+
1114
+static struct omap_hwmod_ocp_if dm81xx_l4_ls__mcspi4 = {
1115
+	.master		= &dm81xx_l4_ls_hwmod,
1116
+	.slave		= &dm81xx_mcspi4_hwmod,
1139
1117
 	.clk		= "sysclk6_ck",
1140
1118
 	.user		= OCP_USER_MPU,
1141
1119
 };
..
..
@@ -1210,154 +1188,6 @@
1210
1188
 	.user		= OCP_USER_MPU,
1211
1189
 };
1212
1190
 
1213
-static struct omap_hwmod_class dm81xx_tpcc_hwmod_class = {
1214
-	.name		= "tpcc",
1215
-};
1216
-
1217
-static struct omap_hwmod dm81xx_tpcc_hwmod = {
1218
-	.name		= "tpcc",
1219
-	.class		= &dm81xx_tpcc_hwmod_class,
1220
-	.clkdm_name	= "alwon_l3s_clkdm",
1221
-	.main_clk	= "sysclk4_ck",
1222
-	.prcm		= {
1223
-		.omap4	= {
1224
-			.clkctrl_offs	= DM81XX_CM_ALWON_TPCC_CLKCTRL,
1225
-			.modulemode	= MODULEMODE_SWCTRL,
1226
-		},
1227
-	},
1228
-};
1229
-
1230
-static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tpcc = {
1231
-	.master		= &dm81xx_alwon_l3_fast_hwmod,
1232
-	.slave		= &dm81xx_tpcc_hwmod,
1233
-	.clk		= "sysclk4_ck",
1234
-	.user		= OCP_USER_MPU,
1235
-};
1236
-
1237
-static struct omap_hwmod_class dm81xx_tptc0_hwmod_class = {
1238
-	.name		= "tptc0",
1239
-};
1240
-
1241
-static struct omap_hwmod dm81xx_tptc0_hwmod = {
1242
-	.name		= "tptc0",
1243
-	.class		= &dm81xx_tptc0_hwmod_class,
1244
-	.clkdm_name	= "alwon_l3s_clkdm",
1245
-	.main_clk	= "sysclk4_ck",
1246
-	.prcm		= {
1247
-		.omap4	= {
1248
-			.clkctrl_offs	= DM81XX_CM_ALWON_TPTC0_CLKCTRL,
1249
-			.modulemode	= MODULEMODE_SWCTRL,
1250
-		},
1251
-	},
1252
-};
1253
-
1254
-static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tptc0 = {
1255
-	.master		= &dm81xx_alwon_l3_fast_hwmod,
1256
-	.slave		= &dm81xx_tptc0_hwmod,
1257
-	.clk		= "sysclk4_ck",
1258
-	.user		= OCP_USER_MPU,
1259
-};
1260
-
1261
-static struct omap_hwmod_ocp_if dm81xx_tptc0__alwon_l3_fast = {
1262
-	.master		= &dm81xx_tptc0_hwmod,
1263
-	.slave		= &dm81xx_alwon_l3_fast_hwmod,
1264
-	.clk		= "sysclk4_ck",
1265
-	.user		= OCP_USER_MPU,
1266
-};
1267
-
1268
-static struct omap_hwmod_class dm81xx_tptc1_hwmod_class = {
1269
-	.name		= "tptc1",
1270
-};
1271
-
1272
-static struct omap_hwmod dm81xx_tptc1_hwmod = {
1273
-	.name		= "tptc1",
1274
-	.class		= &dm81xx_tptc1_hwmod_class,
1275
-	.clkdm_name	= "alwon_l3s_clkdm",
1276
-	.main_clk	= "sysclk4_ck",
1277
-	.prcm		= {
1278
-		.omap4	= {
1279
-			.clkctrl_offs	= DM81XX_CM_ALWON_TPTC1_CLKCTRL,
1280
-			.modulemode	= MODULEMODE_SWCTRL,
1281
-		},
1282
-	},
1283
-};
1284
-
1285
-static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tptc1 = {
1286
-	.master		= &dm81xx_alwon_l3_fast_hwmod,
1287
-	.slave		= &dm81xx_tptc1_hwmod,
1288
-	.clk		= "sysclk4_ck",
1289
-	.user		= OCP_USER_MPU,
1290
-};
1291
-
1292
-static struct omap_hwmod_ocp_if dm81xx_tptc1__alwon_l3_fast = {
1293
-	.master		= &dm81xx_tptc1_hwmod,
1294
-	.slave		= &dm81xx_alwon_l3_fast_hwmod,
1295
-	.clk		= "sysclk4_ck",
1296
-	.user		= OCP_USER_MPU,
1297
-};
1298
-
1299
-static struct omap_hwmod_class dm81xx_tptc2_hwmod_class = {
1300
-	.name		= "tptc2",
1301
-};
1302
-
1303
-static struct omap_hwmod dm81xx_tptc2_hwmod = {
1304
-	.name		= "tptc2",
1305
-	.class		= &dm81xx_tptc2_hwmod_class,
1306
-	.clkdm_name	= "alwon_l3s_clkdm",
1307
-	.main_clk	= "sysclk4_ck",
1308
-	.prcm		= {
1309
-		.omap4	= {
1310
-			.clkctrl_offs	= DM81XX_CM_ALWON_TPTC2_CLKCTRL,
1311
-			.modulemode	= MODULEMODE_SWCTRL,
1312
-		},
1313
-	},
1314
-};
1315
-
1316
-static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tptc2 = {
1317
-	.master		= &dm81xx_alwon_l3_fast_hwmod,
1318
-	.slave		= &dm81xx_tptc2_hwmod,
1319
-	.clk		= "sysclk4_ck",
1320
-	.user		= OCP_USER_MPU,
1321
-};
1322
-
1323
-static struct omap_hwmod_ocp_if dm81xx_tptc2__alwon_l3_fast = {
1324
-	.master		= &dm81xx_tptc2_hwmod,
1325
-	.slave		= &dm81xx_alwon_l3_fast_hwmod,
1326
-	.clk		= "sysclk4_ck",
1327
-	.user		= OCP_USER_MPU,
1328
-};
1329
-
1330
-static struct omap_hwmod_class dm81xx_tptc3_hwmod_class = {
1331
-	.name		= "tptc3",
1332
-};
1333
-
1334
-static struct omap_hwmod dm81xx_tptc3_hwmod = {
1335
-	.name		= "tptc3",
1336
-	.class		= &dm81xx_tptc3_hwmod_class,
1337
-	.clkdm_name	= "alwon_l3s_clkdm",
1338
-	.main_clk	= "sysclk4_ck",
1339
-	.prcm		= {
1340
-		.omap4	= {
1341
-			.clkctrl_offs	= DM81XX_CM_ALWON_TPTC3_CLKCTRL,
1342
-			.modulemode	= MODULEMODE_SWCTRL,
1343
-		},
1344
-	},
1345
-};
1346
-
1347
-static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tptc3 = {
1348
-	.master		= &dm81xx_alwon_l3_fast_hwmod,
1349
-	.slave		= &dm81xx_tptc3_hwmod,
1350
-	.clk		= "sysclk4_ck",
1351
-	.user		= OCP_USER_MPU,
1352
-};
1353
-
1354
-static struct omap_hwmod_ocp_if dm81xx_tptc3__alwon_l3_fast = {
1355
-	.master		= &dm81xx_tptc3_hwmod,
1356
-	.slave		= &dm81xx_alwon_l3_fast_hwmod,
1357
-	.clk		= "sysclk4_ck",
1358
-	.user		= OCP_USER_MPU,
1359
-};
1360
-
1361
1191
 /*
1362
1192
  * REVISIT: Test and enable the following once clocks work:
1363
1193
  * dm81xx_l4_ls__mailbox
..
..
@@ -1378,24 +1208,16 @@
1378
1208
 	&dm81xx_l4_ls__i2c2,
1379
1209
 	&dm81xx_l4_ls__gpio1,
1380
1210
 	&dm81xx_l4_ls__gpio2,
1211
+	&dm81xx_l4_ls__gpio3,
1212
+	&dm81xx_l4_ls__gpio4,
1381
1213
 	&dm81xx_l4_ls__elm,
1382
1214
 	&dm81xx_l4_ls__mcspi1,
1215
+	&dm81xx_l4_ls__mcspi2,
1216
+	&dm81xx_l4_ls__mcspi3,
1217
+	&dm81xx_l4_ls__mcspi4,
1383
1218
 	&dm814x_l4_ls__mmc1,
1384
1219
 	&dm814x_l4_ls__mmc2,
1385
1220
 	&ti81xx_l4_ls__rtc,
1386
-	&dm81xx_alwon_l3_fast__tpcc,
1387
-	&dm81xx_alwon_l3_fast__tptc0,
1388
-	&dm81xx_alwon_l3_fast__tptc1,
1389
-	&dm81xx_alwon_l3_fast__tptc2,
1390
-	&dm81xx_alwon_l3_fast__tptc3,
1391
-	&dm81xx_tptc0__alwon_l3_fast,
1392
-	&dm81xx_tptc1__alwon_l3_fast,
1393
-	&dm81xx_tptc2__alwon_l3_fast,
1394
-	&dm81xx_tptc3__alwon_l3_fast,
1395
-	&dm814x_l4_ls__timer1,
1396
-	&dm814x_l4_ls__timer2,
1397
-	&dm814x_l4_hs__cpgmac0,
1398
-	&dm814x_cpgmac0__mdio,
1399
1221
 	&dm81xx_alwon_l3_slow__gpmc,
1400
1222
 	&dm814x_default_l3_slow__usbss,
1401
1223
 	&dm814x_alwon_l3_med__mmc3,
..
..
@@ -1424,8 +1246,6 @@
1424
1246
 	&dm81xx_l4_ls__elm,
1425
1247
 	&ti81xx_l4_ls__rtc,
1426
1248
 	&dm816x_l4_ls__mmc1,
1427
-	&dm816x_l4_ls__timer1,
1428
-	&dm816x_l4_ls__timer2,
1429
1249
 	&dm816x_l4_ls__timer3,
1430
1250
 	&dm816x_l4_ls__timer4,
1431
1251
 	&dm816x_l4_ls__timer5,
..
..
@@ -1438,15 +1258,6 @@
1438
1258
 	&dm81xx_emac0__mdio,
1439
1259
 	&dm816x_l4_hs__emac1,
1440
1260
 	&dm81xx_l4_hs__sata,
1441
-	&dm81xx_alwon_l3_fast__tpcc,
1442
-	&dm81xx_alwon_l3_fast__tptc0,
1443
-	&dm81xx_alwon_l3_fast__tptc1,
1444
-	&dm81xx_alwon_l3_fast__tptc2,
1445
-	&dm81xx_alwon_l3_fast__tptc3,
1446
-	&dm81xx_tptc0__alwon_l3_fast,
1447
-	&dm81xx_tptc1__alwon_l3_fast,
1448
-	&dm81xx_tptc2__alwon_l3_fast,
1449
-	&dm81xx_tptc3__alwon_l3_fast,
1450
1261
 	&dm81xx_alwon_l3_slow__gpmc,
1451
1262
 	&dm816x_default_l3_slow__usbss,
1452
1263
 	NULL,