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2024-02-20 102a0743326a03cd1a1202ceda21e175b7d3575c 
 kernel/arch/arm/boot/dts/omap4.dtsi
....@@ -1,9 +1,6 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
12 /*
2
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
3
- *
4
- * This program is free software; you can redistribute it and/or modify
5
- * it under the terms of the GNU General Public License version 2 as
6
- * published by the Free Software Foundation.
3
+ * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
74  */
85 
96 #include <dt-bindings/bus/ti-sysc.h>
....@@ -34,6 +31,8 @@
3431 		serial1 = &uart2;
3532 		serial2 = &uart3;
3633 		serial3 = &uart4;
34
+		rproc0 = &dsp;
35
+		rproc1 = &ipu;
3736 	};
3837 
3938 	cpus {
....@@ -79,7 +78,7 @@
7978 		interrupt-parent = <&gic>;
8079 	};
8180 
82
-	L2: l2-cache-controller@48242000 {
81
+	L2: cache-controller@48242000 {
8382 		compatible = "arm,pl310-cache";
8483 		reg = <0x48242000 0x1000>;
8584 		cache-unified;
....@@ -112,11 +111,6 @@
112111 			compatible = "ti,omap4-mpu";
113112 			ti,hwmods = "mpu";
114113 			sram = <&ocmcram>;
115
-		};
116
-
117
-		dsp {
118
-			compatible = "ti,omap3-c64";
119
-			ti,hwmods = "dsp";
120114 		};
121115 
122116 		iva {
....@@ -153,7 +147,10 @@
153147 		l4_per: interconnect@48000000 {
154148 		};
155149 
156
-		ocmcram: ocmcram@40304000 {
150
+		l4_abe: interconnect@40100000 {
151
+		};
152
+
153
+		ocmcram: sram@40304000 {
157154 			compatible = "mmio-sram";
158155 			reg = <0x40304000 0xa000>; /* 40k */
159156 		};
....@@ -176,14 +173,6 @@
176173 			#interrupt-cells = <2>;
177174 			gpio-controller;
178175 			#gpio-cells = <2>;
179
-		};
180
-
181
-		mmu_dsp: mmu@4a066000 {
182
-			compatible = "ti,omap4-iommu";
183
-			reg = <0x4a066000 0x100>;
184
-			interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
185
-			ti,hwmods = "mmu_dsp";
186
-			#iommu-cells = <0>;
187176 		};
188177 
189178 		target-module@52000000 {
....@@ -211,141 +200,37 @@
211200 			/* No child device binding, driver in staging */
212201 		};
213202 
214
-		mmu_ipu: mmu@55082000 {
215
-			compatible = "ti,omap4-iommu";
216
-			reg = <0x55082000 0x100>;
217
-			interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
218
-			ti,hwmods = "mmu_ipu";
219
-			#iommu-cells = <0>;
220
-			ti,iommu-bus-err-back;
221
-		};
222
-		target-module@40130000 {
203
+		target-module@55082000 {
223204 			compatible = "ti,sysc-omap2", "ti,sysc";
224
-			ti,hwmods = "wd_timer3";
225
-			reg = <0x40130000 0x4>,
226
-			      <0x40130010 0x4>,
227
-			      <0x40130014 0x4>;
205
+			reg = <0x55082000 0x4>,
206
+			      <0x55082010 0x4>,
207
+			      <0x55082014 0x4>;
228208 			reg-names = "rev", "sysc", "syss";
229
-			ti,sysc-mask = <(SYSC_OMAP2_EMUFREE |
230
-					 SYSC_OMAP2_SOFTRESET)>;
231209 			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
232210 					<SYSC_IDLE_NO>,
233
-					<SYSC_IDLE_SMART>,
234
-					<SYSC_IDLE_SMART_WKUP>;
235
-			ti,syss-mask = <1>;
236
-			/* Domains (V, P, C): abe, abe_pwrdm, abe_clkdm */
237
-			clocks = <&abe_clkctrl OMAP4_WD_TIMER3_CLKCTRL 0>;
211
+					<SYSC_IDLE_SMART>;
212
+			ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
213
+					 SYSC_OMAP2_SOFTRESET |
214
+					 SYSC_OMAP2_AUTOIDLE)>;
215
+			clocks = <&ducati_clkctrl OMAP4_IPU_CLKCTRL 0>;
238216 			clock-names = "fck";
239
-			#address-cells = <1>;
217
+			resets = <&prm_core 2>;
218
+			reset-names = "rstctrl";
219
+			ranges = <0x0 0x55082000 0x100>;
240220 			#size-cells = <1>;
241
-			ranges = <0x00000000 0x40130000 0x1000>, /* MPU private access */
242
-				 <0x49030000 0x49030000 0x0080>; /* L3 Interconnect */
221
+			#address-cells = <1>;
243222 
244
-			wdt3: wdt@0 {
245
-				compatible = "ti,omap4-wdt", "ti,omap3-wdt";
246
-				reg = <0x0 0x80>;
247
-				interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
223
+			mmu_ipu: mmu@0 {
224
+				compatible = "ti,omap4-iommu";
225
+				reg = <0x0 0x100>;
226
+				interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
227
+				#iommu-cells = <0>;
228
+				ti,iommu-bus-err-back;
248229 			};
249
-		};
250
-
251
-		mcpdm: mcpdm@40132000 {
252
-			compatible = "ti,omap4-mcpdm";
253
-			reg = <0x40132000 0x7f>, /* MPU private access */
254
-			      <0x49032000 0x7f>; /* L3 Interconnect */
255
-			reg-names = "mpu", "dma";
256
-			interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
257
-			ti,hwmods = "mcpdm";
258
-			dmas = <&sdma 65>,
259
-			       <&sdma 66>;
260
-			dma-names = "up_link", "dn_link";
261
-			status = "disabled";
262
-		};
263
-
264
-		dmic: dmic@4012e000 {
265
-			compatible = "ti,omap4-dmic";
266
-			reg = <0x4012e000 0x7f>, /* MPU private access */
267
-			      <0x4902e000 0x7f>; /* L3 Interconnect */
268
-			reg-names = "mpu", "dma";
269
-			interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
270
-			ti,hwmods = "dmic";
271
-			dmas = <&sdma 67>;
272
-			dma-names = "up_link";
273
-			status = "disabled";
274
-		};
275
-
276
-		mcbsp1: mcbsp@40122000 {
277
-			compatible = "ti,omap4-mcbsp";
278
-			reg = <0x40122000 0xff>, /* MPU private access */
279
-			      <0x49022000 0xff>; /* L3 Interconnect */
280
-			reg-names = "mpu", "dma";
281
-			interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
282
-			interrupt-names = "common";
283
-			ti,buffer-size = <128>;
284
-			ti,hwmods = "mcbsp1";
285
-			dmas = <&sdma 33>,
286
-			       <&sdma 34>;
287
-			dma-names = "tx", "rx";
288
-			status = "disabled";
289
-		};
290
-
291
-		mcbsp2: mcbsp@40124000 {
292
-			compatible = "ti,omap4-mcbsp";
293
-			reg = <0x40124000 0xff>, /* MPU private access */
294
-			      <0x49024000 0xff>; /* L3 Interconnect */
295
-			reg-names = "mpu", "dma";
296
-			interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
297
-			interrupt-names = "common";
298
-			ti,buffer-size = <128>;
299
-			ti,hwmods = "mcbsp2";
300
-			dmas = <&sdma 17>,
301
-			       <&sdma 18>;
302
-			dma-names = "tx", "rx";
303
-			status = "disabled";
304
-		};
305
-
306
-		mcbsp3: mcbsp@40126000 {
307
-			compatible = "ti,omap4-mcbsp";
308
-			reg = <0x40126000 0xff>, /* MPU private access */
309
-			      <0x49026000 0xff>; /* L3 Interconnect */
310
-			reg-names = "mpu", "dma";
311
-			interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
312
-			interrupt-names = "common";
313
-			ti,buffer-size = <128>;
314
-			ti,hwmods = "mcbsp3";
315
-			dmas = <&sdma 19>,
316
-			       <&sdma 20>;
317
-			dma-names = "tx", "rx";
318
-			status = "disabled";
319
-		};
320
-
321
-		target-module@40128000 {
322
-			compatible = "ti,sysc-mcasp", "ti,sysc";
323
-			ti,hwmods = "mcasp";
324
-			reg = <0x40128000 0x4>,
325
-			      <0x40128004 0x4>;
326
-			reg-names = "rev", "sysc";
327
-			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
328
-					<SYSC_IDLE_NO>,
329
-					<SYSC_IDLE_SMART>,
330
-					<SYSC_IDLE_SMART_WKUP>;
331
-			clocks = <&abe_clkctrl OMAP4_MCASP_CLKCTRL 0>;
332
-			clock-names = "fck";
333
-			#address-cells = <1>;
334
-			#size-cells = <1>;
335
-			ranges = <0x00000000 0x40128000 0x1000>, /* MPU */
336
-				 <0x49028000 0x49028000 0x1000>; /* L3 */
337
-
338
-			/*
339
-			 * Child device unsupported by davinci-mcasp. At least
340
-			 * RX path is disabled for omap4, and only DIT mode
341
-			 * works with no I2S. See also old Android kernel
342
-			 * omap-mcasp driver for more information.
343
-			 */
344230 		};
345231 
346232 		target-module@4012c000 {
347233 			compatible = "ti,sysc-omap4", "ti,sysc";
348
-			ti,hwmods = "slimbus1";
349234 			reg = <0x4012c000 0x4>,
350235 			      <0x4012c010 0x4>;
351236 			reg-names = "rev", "sysc";
....@@ -362,33 +247,6 @@
362247 				 <0x4902c000 0x4902c000 0x1000>; /* L3 */
363248 
364249 			/* No child device binding or driver in mainline */
365
-		};
366
-
367
-		target-module@401f1000 {
368
-			compatible = "ti,sysc-omap4", "ti,sysc";
369
-			ti,hwmods = "aess";
370
-			reg = <0x401f1000 0x4>,
371
-			      <0x401f1010 0x4>;
372
-			reg-names = "rev", "sysc";
373
-			ti,sysc-midle = <SYSC_IDLE_FORCE>,
374
-					<SYSC_IDLE_NO>,
375
-					<SYSC_IDLE_SMART>,
376
-					<SYSC_IDLE_SMART_WKUP>;
377
-			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
378
-					<SYSC_IDLE_NO>,
379
-					<SYSC_IDLE_SMART>;
380
-			clocks = <&abe_clkctrl OMAP4_AESS_CLKCTRL 0>;
381
-			clock-names = "fck";
382
-			#address-cells = <1>;
383
-			#size-cells = <1>;
384
-			ranges = <0x00000000 0x401f1000 0x1000>, /* MPU */
385
-				 <0x490f1000 0x490f1000 0x1000>; /* L3 */
386
-
387
-			/*
388
-			 * No child device binding or driver in mainline.
389
-			 * See Android tree and related upstreaming efforts
390
-			 * for the old driver.
391
-			 */
392250 		};
393251 
394252 		dmm@4e000000 {
....@@ -422,77 +280,113 @@
422280 			hw-caps-temp-alert;
423281 		};
424282 
425
-		timer5: timer@40138000 {
426
-			compatible = "ti,omap4430-timer";
427
-			reg = <0x40138000 0x80>,
428
-			      <0x49038000 0x80>;
429
-			interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
430
-			ti,hwmods = "timer5";
431
-			ti,timer-dsp;
283
+		dsp: dsp {
284
+			compatible = "ti,omap4-dsp";
285
+			ti,bootreg = <&scm_conf 0x304 0>;
286
+			iommus = <&mmu_dsp>;
287
+			resets = <&prm_tesla 0>;
288
+			clocks = <&tesla_clkctrl OMAP4_DSP_CLKCTRL 0>;
289
+			firmware-name = "omap4-dsp-fw.xe64T";
290
+			mboxes = <&mailbox &mbox_dsp>;
291
+			status = "disabled";
432292 		};
433293 
434
-		timer6: timer@4013a000 {
435
-			compatible = "ti,omap4430-timer";
436
-			reg = <0x4013a000 0x80>,
437
-			      <0x4903a000 0x80>;
438
-			interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
439
-			ti,hwmods = "timer6";
440
-			ti,timer-dsp;
294
+		ipu: ipu@55020000 {
295
+			compatible = "ti,omap4-ipu";
296
+			reg = <0x55020000 0x10000>;
297
+			reg-names = "l2ram";
298
+			iommus = <&mmu_ipu>;
299
+			resets = <&prm_core 0>, <&prm_core 1>;
300
+			clocks = <&ducati_clkctrl OMAP4_IPU_CLKCTRL 0>;
301
+			firmware-name = "omap4-ipu-fw.xem3";
302
+			mboxes = <&mailbox &mbox_ipu>;
303
+			status = "disabled";
441304 		};
442305 
443
-		timer7: timer@4013c000 {
444
-			compatible = "ti,omap4430-timer";
445
-			reg = <0x4013c000 0x80>,
446
-			      <0x4903c000 0x80>;
447
-			interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
448
-			ti,hwmods = "timer7";
449
-			ti,timer-dsp;
306
+		aes1_target: target-module@4b501000 {
307
+			compatible = "ti,sysc-omap2", "ti,sysc";
308
+			reg = <0x4b501080 0x4>,
309
+			      <0x4b501084 0x4>,
310
+			      <0x4b501088 0x4>;
311
+			reg-names = "rev", "sysc", "syss";
312
+			ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
313
+					 SYSC_OMAP2_AUTOIDLE)>;
314
+			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
315
+					<SYSC_IDLE_NO>,
316
+					<SYSC_IDLE_SMART>,
317
+					<SYSC_IDLE_SMART_WKUP>;
318
+			ti,syss-mask = <1>;
319
+			/* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */
320
+			clocks = <&l4_secure_clkctrl OMAP4_AES1_CLKCTRL 0>;
321
+			clock-names = "fck";
322
+			#address-cells = <1>;
323
+			#size-cells = <1>;
324
+			ranges = <0x0 0x4b501000 0x1000>;
325
+
326
+			aes1: aes@0 {
327
+				compatible = "ti,omap4-aes";
328
+				reg = <0 0xa0>;
329
+				interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
330
+				dmas = <&sdma 111>, <&sdma 110>;
331
+				dma-names = "tx", "rx";
332
+			};
450333 		};
451334 
452
-		timer8: timer@4013e000 {
453
-			compatible = "ti,omap4430-timer";
454
-			reg = <0x4013e000 0x80>,
455
-			      <0x4903e000 0x80>;
456
-			interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
457
-			ti,hwmods = "timer8";
458
-			ti,timer-pwm;
459
-			ti,timer-dsp;
335
+		aes2_target: target-module@4b701000 {
336
+			compatible = "ti,sysc-omap2", "ti,sysc";
337
+			reg = <0x4b701080 0x4>,
338
+			      <0x4b701084 0x4>,
339
+			      <0x4b701088 0x4>;
340
+			reg-names = "rev", "sysc", "syss";
341
+			ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
342
+					 SYSC_OMAP2_AUTOIDLE)>;
343
+			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
344
+					<SYSC_IDLE_NO>,
345
+					<SYSC_IDLE_SMART>,
346
+					<SYSC_IDLE_SMART_WKUP>;
347
+			ti,syss-mask = <1>;
348
+			/* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */
349
+			clocks = <&l4_secure_clkctrl OMAP4_AES2_CLKCTRL 0>;
350
+			clock-names = "fck";
351
+			#address-cells = <1>;
352
+			#size-cells = <1>;
353
+			ranges = <0x0 0x4b701000 0x1000>;
354
+
355
+			aes2: aes@0 {
356
+				compatible = "ti,omap4-aes";
357
+				reg = <0 0xa0>;
358
+				interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
359
+				dmas = <&sdma 114>, <&sdma 113>;
360
+				dma-names = "tx", "rx";
361
+			};
460362 		};
461363 
462
-		aes1: aes@4b501000 {
463
-			compatible = "ti,omap4-aes";
464
-			ti,hwmods = "aes1";
465
-			reg = <0x4b501000 0xa0>;
466
-			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
467
-			dmas = <&sdma 111>, <&sdma 110>;
468
-			dma-names = "tx", "rx";
469
-		};
364
+		sham_target: target-module@4b100000 {
365
+			compatible = "ti,sysc-omap3-sham", "ti,sysc";
366
+			reg = <0x4b100100 0x4>,
367
+			      <0x4b100110 0x4>,
368
+			      <0x4b100114 0x4>;
369
+			reg-names = "rev", "sysc", "syss";
370
+			ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
371
+					 SYSC_OMAP2_AUTOIDLE)>;
372
+			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
373
+					<SYSC_IDLE_NO>,
374
+					<SYSC_IDLE_SMART>;
375
+			ti,syss-mask = <1>;
376
+			/* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */
377
+			clocks = <&l4_secure_clkctrl OMAP4_SHA2MD5_CLKCTRL 0>;
378
+			clock-names = "fck";
379
+			#address-cells = <1>;
380
+			#size-cells = <1>;
381
+			ranges = <0x0 0x4b100000 0x1000>;
470382 
471
-		aes2: aes@4b701000 {
472
-			compatible = "ti,omap4-aes";
473
-			ti,hwmods = "aes2";
474
-			reg = <0x4b701000 0xa0>;
475
-			interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
476
-			dmas = <&sdma 114>, <&sdma 113>;
477
-			dma-names = "tx", "rx";
478
-		};
479
-
480
-		des: des@480a5000 {
481
-			compatible = "ti,omap4-des";
482
-			ti,hwmods = "des";
483
-			reg = <0x480a5000 0xa0>;
484
-			interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
485
-			dmas = <&sdma 117>, <&sdma 116>;
486
-			dma-names = "tx", "rx";
487
-		};
488
-
489
-		sham: sham@4b100000 {
490
-			compatible = "ti,omap4-sham";
491
-			ti,hwmods = "sham";
492
-			reg = <0x4b100000 0x300>;
493
-			interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
494
-			dmas = <&sdma 119>;
495
-			dma-names = "rx";
383
+			sham: sham@0 {
384
+				compatible = "ti,omap4-sham";
385
+				reg = <0 0x300>;
386
+				interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
387
+				dmas = <&sdma 119>;
388
+				dma-names = "rx";
389
+			};
496390 		};
497391 
498392 		abb_mpu: regulator-abb-mpu {
....@@ -523,9 +417,8 @@
523417 
524418 		sgx_module: target-module@56000000 {
525419 			compatible = "ti,sysc-omap4", "ti,sysc";
526
-			ti,hwmods = "gpu";
527
-			reg = <0x5601fc00 0x4>,
528
-			      <0x5601fc10 0x4>;
420
+			reg = <0x5600fe00 0x4>,
421
+			      <0x5600fe10 0x4>;
529422 			reg-names = "rev", "sysc";
530423 			ti,sysc-midle = <SYSC_IDLE_FORCE>,
531424 					<SYSC_IDLE_NO>,
....@@ -547,91 +440,266 @@
547440 			 */
548441 		};
549442 
550
-		dss: dss@58000000 {
551
-			compatible = "ti,omap4-dss";
552
-			reg = <0x58000000 0x80>;
553
-			status = "disabled";
554
-			ti,hwmods = "dss_core";
555
-			clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>;
556
-			clock-names = "fck";
443
+		/*
444
+		 * DSS is only using l3 mapping without l4 as noted in the TRM
445
+		 * "10.1.3 DSS Register Manual" for omap4460.
446
+		 */
447
+		target-module@58000000 {
448
+			compatible = "ti,sysc-omap2", "ti,sysc";
449
+			reg = <0x58000000 4>,
450
+			      <0x58000014 4>;
451
+			reg-names = "rev", "syss";
452
+			ti,syss-mask = <1>;
453
+			clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 0>,
454
+				 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 9>,
455
+				 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>,
456
+				 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 11>;
457
+			clock-names = "fck", "hdmi_clk", "sys_clk", "tv_clk";
557458 			#address-cells = <1>;
558459 			#size-cells = <1>;
559
-			ranges;
460
+			ranges = <0 0x58000000 0x1000000>;
560461 
561
-			dispc@58001000 {
562
-				compatible = "ti,omap4-dispc";
563
-				reg = <0x58001000 0x1000>;
564
-				interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
565
-				ti,hwmods = "dss_dispc";
462
+			dss: dss@0 {
463
+				compatible = "ti,omap4-dss";
464
+				reg = <0 0x80>;
465
+				status = "disabled";
566466 				clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>;
567467 				clock-names = "fck";
568
-			};
468
+				#address-cells = <1>;
469
+				#size-cells = <1>;
470
+				ranges = <0 0 0x1000000>;
569471 
570
-			rfbi: encoder@58002000  {
571
-				compatible = "ti,omap4-rfbi";
572
-				reg = <0x58002000 0x1000>;
573
-				status = "disabled";
574
-				ti,hwmods = "dss_rfbi";
575
-				clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>, <&l3_div_ck>;
576
-				clock-names = "fck", "ick";
577
-			};
472
+				target-module@1000 {
473
+					compatible = "ti,sysc-omap2", "ti,sysc";
474
+					reg = <0x1000 0x4>,
475
+					      <0x1010 0x4>,
476
+					      <0x1014 0x4>;
477
+					reg-names = "rev", "sysc", "syss";
478
+					ti,sysc-sidle = <SYSC_IDLE_FORCE>,
479
+							<SYSC_IDLE_NO>,
480
+							<SYSC_IDLE_SMART>;
481
+					ti,sysc-midle = <SYSC_IDLE_FORCE>,
482
+							<SYSC_IDLE_NO>,
483
+							<SYSC_IDLE_SMART>;
484
+					ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
485
+							 SYSC_OMAP2_ENAWAKEUP |
486
+							 SYSC_OMAP2_SOFTRESET |
487
+							 SYSC_OMAP2_AUTOIDLE)>;
488
+					ti,syss-mask = <1>;
489
+					clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>,
490
+						 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
491
+					clock-names = "fck", "sys_clk";
492
+					#address-cells = <1>;
493
+					#size-cells = <1>;
494
+					ranges = <0 0x1000 0x1000>;
578495 
579
-			venc: encoder@58003000 {
580
-				compatible = "ti,omap4-venc";
581
-				reg = <0x58003000 0x1000>;
582
-				status = "disabled";
583
-				ti,hwmods = "dss_venc";
584
-				clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 11>;
585
-				clock-names = "fck";
586
-			};
496
+					dispc@0 {
497
+						compatible = "ti,omap4-dispc";
498
+						reg = <0 0x1000>;
499
+						interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
500
+						clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>;
501
+						clock-names = "fck";
502
+					};
503
+				};
587504 
588
-			dsi1: encoder@58004000 {
589
-				compatible = "ti,omap4-dsi";
590
-				reg = <0x58004000 0x200>,
591
-				      <0x58004200 0x40>,
592
-				      <0x58004300 0x20>;
593
-				reg-names = "proto", "phy", "pll";
594
-				interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
595
-				status = "disabled";
596
-				ti,hwmods = "dss_dsi1";
597
-				clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>,
598
-					 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
599
-				clock-names = "fck", "sys_clk";
600
-			};
505
+				target-module@2000 {
506
+					compatible = "ti,sysc-omap2", "ti,sysc";
507
+					reg = <0x2000 0x4>,
508
+					      <0x2010 0x4>,
509
+					      <0x2014 0x4>;
510
+					reg-names = "rev", "sysc", "syss";
511
+					ti,sysc-sidle = <SYSC_IDLE_FORCE>,
512
+							<SYSC_IDLE_NO>,
513
+							<SYSC_IDLE_SMART>;
514
+					ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
515
+							 SYSC_OMAP2_AUTOIDLE)>;
516
+					ti,syss-mask = <1>;
517
+					clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>,
518
+						 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
519
+					clock-names = "fck", "sys_clk";
520
+					#address-cells = <1>;
521
+					#size-cells = <1>;
522
+					ranges = <0 0x2000 0x1000>;
601523 
602
-			dsi2: encoder@58005000 {
603
-				compatible = "ti,omap4-dsi";
604
-				reg = <0x58005000 0x200>,
605
-				      <0x58005200 0x40>,
606
-				      <0x58005300 0x20>;
607
-				reg-names = "proto", "phy", "pll";
608
-				interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
609
-				status = "disabled";
610
-				ti,hwmods = "dss_dsi2";
611
-				clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>,
612
-					 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
613
-				clock-names = "fck", "sys_clk";
614
-			};
524
+					rfbi: encoder@0  {
525
+						reg = <0 0x1000>;
526
+						status = "disabled";
527
+						clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>, <&l3_div_ck>;
528
+						clock-names = "fck", "ick";
529
+					};
530
+				};
615531 
616
-			hdmi: encoder@58006000 {
617
-				compatible = "ti,omap4-hdmi";
618
-				reg = <0x58006000 0x200>,
619
-				      <0x58006200 0x100>,
620
-				      <0x58006300 0x100>,
621
-				      <0x58006400 0x1000>;
622
-				reg-names = "wp", "pll", "phy", "core";
623
-				interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
624
-				status = "disabled";
625
-				ti,hwmods = "dss_hdmi";
626
-				clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 9>,
627
-					 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
628
-				clock-names = "fck", "sys_clk";
629
-				dmas = <&sdma 76>;
630
-				dma-names = "audio_tx";
532
+				target-module@3000 {
533
+					compatible = "ti,sysc-omap2", "ti,sysc";
534
+					reg = <0x3000 0x4>;
535
+					reg-names = "rev";
536
+					clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
537
+					clock-names = "sys_clk";
538
+					#address-cells = <1>;
539
+					#size-cells = <1>;
540
+					ranges = <0 0x3000 0x1000>;
541
+
542
+					venc: encoder@0 {
543
+						compatible = "ti,omap4-venc";
544
+						reg = <0 0x1000>;
545
+						status = "disabled";
546
+						clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 11>;
547
+						clock-names = "fck";
548
+					};
549
+				};
550
+
551
+				target-module@4000 {
552
+					compatible = "ti,sysc-omap2", "ti,sysc";
553
+					reg = <0x4000 0x4>,
554
+					      <0x4010 0x4>,
555
+					      <0x4014 0x4>;
556
+					reg-names = "rev", "sysc", "syss";
557
+					ti,sysc-sidle = <SYSC_IDLE_FORCE>,
558
+							<SYSC_IDLE_NO>,
559
+							<SYSC_IDLE_SMART>;
560
+					ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
561
+							 SYSC_OMAP2_ENAWAKEUP |
562
+							 SYSC_OMAP2_SOFTRESET |
563
+							 SYSC_OMAP2_AUTOIDLE)>;
564
+					ti,syss-mask = <1>;
565
+					#address-cells = <1>;
566
+					#size-cells = <1>;
567
+					ranges = <0 0x4000 0x1000>;
568
+
569
+					dsi1: encoder@0 {
570
+						compatible = "ti,omap4-dsi";
571
+						reg = <0 0x200>,
572
+						      <0x200 0x40>,
573
+						      <0x300 0x20>;
574
+						reg-names = "proto", "phy", "pll";
575
+						interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
576
+						status = "disabled";
577
+						clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>,
578
+							 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
579
+						clock-names = "fck", "sys_clk";
580
+
581
+						#address-cells = <1>;
582
+						#size-cells = <0>;
583
+					};
584
+				};
585
+
586
+				target-module@5000 {
587
+					compatible = "ti,sysc-omap2", "ti,sysc";
588
+					reg = <0x5000 0x4>,
589
+					      <0x5010 0x4>,
590
+					      <0x5014 0x4>;
591
+					reg-names = "rev", "sysc", "syss";
592
+					ti,sysc-sidle = <SYSC_IDLE_FORCE>,
593
+							<SYSC_IDLE_NO>,
594
+							<SYSC_IDLE_SMART>;
595
+					ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
596
+							 SYSC_OMAP2_ENAWAKEUP |
597
+							 SYSC_OMAP2_SOFTRESET |
598
+							 SYSC_OMAP2_AUTOIDLE)>;
599
+					ti,syss-mask = <1>;
600
+					#address-cells = <1>;
601
+					#size-cells = <1>;
602
+					ranges = <0 0x5000 0x1000>;
603
+
604
+					dsi2: encoder@0 {
605
+						compatible = "ti,omap4-dsi";
606
+						reg = <0 0x200>,
607
+						      <0x200 0x40>,
608
+						      <0x300 0x20>;
609
+						reg-names = "proto", "phy", "pll";
610
+						interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
611
+						status = "disabled";
612
+						clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>,
613
+						         <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
614
+						clock-names = "fck", "sys_clk";
615
+
616
+						#address-cells = <1>;
617
+						#size-cells = <0>;
618
+					};
619
+				};
620
+
621
+				target-module@6000 {
622
+					compatible = "ti,sysc-omap4", "ti,sysc";
623
+					reg = <0x6000 0x4>,
624
+					      <0x6010 0x4>;
625
+					reg-names = "rev", "sysc";
626
+					/*
627
+					 * Has SYSC_IDLE_SMART and SYSC_IDLE_SMART_WKUP
628
+					 * but HDMI audio will fail with them.
629
+					 */
630
+					ti,sysc-sidle = <SYSC_IDLE_FORCE>,
631
+							<SYSC_IDLE_NO>;
632
+					ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET)>;
633
+					clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 9>,
634
+						 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>;
635
+					clock-names = "fck", "dss_clk";
636
+					#address-cells = <1>;
637
+					#size-cells = <1>;
638
+					ranges = <0 0x6000 0x2000>;
639
+
640
+					hdmi: encoder@0 {
641
+					compatible = "ti,omap4-hdmi";
642
+						reg = <0 0x200>,
643
+						      <0x200 0x100>,
644
+						      <0x300 0x100>,
645
+						      <0x400 0x1000>;
646
+						reg-names = "wp", "pll", "phy", "core";
647
+						interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
648
+						status = "disabled";
649
+						clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 9>,
650
+						         <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
651
+						clock-names = "fck", "sys_clk";
652
+						dmas = <&sdma 76>;
653
+						dma-names = "audio_tx";
654
+					};
655
+				};
631656 			};
632657 		};
633658 	};
634659 };
635660 
636661 #include "omap4-l4.dtsi"
662
+#include "omap4-l4-abe.dtsi"
637663 #include "omap44xx-clocks.dtsi"
664
+
665
+&prm {
666
+	prm_tesla: prm@400 {
667
+		compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
668
+		reg = <0x400 0x100>;
669
+		#reset-cells = <1>;
670
+	};
671
+
672
+	prm_abe: prm@500 {
673
+		compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
674
+		reg = <0x500 0x100>;
675
+		#power-domain-cells = <0>;
676
+	};
677
+
678
+	prm_core: prm@700 {
679
+		compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
680
+		reg = <0x700 0x100>;
681
+		#reset-cells = <1>;
682
+	};
683
+
684
+	prm_ivahd: prm@f00 {
685
+		compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
686
+		reg = <0xf00 0x100>;
687
+		#reset-cells = <1>;
688
+	};
689
+
690
+	prm_device: prm@1b00 {
691
+		compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
692
+		reg = <0x1b00 0x40>;
693
+		#reset-cells = <1>;
694
+	};
695
+};
696
+
697
+/* Preferred always-on timer for clockevent */
698
+&timer1_target {
699
+	ti,no-reset-on-init;
700
+	ti,no-idle;
701
+	timer@0 {
702
+		assigned-clocks = <&l4_wkup_clkctrl OMAP4_TIMER1_CLKCTRL 24>;
703
+		assigned-clock-parents = <&sys_32k_ck>;
704
+	};
705
+};