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| 1 | +/* SPDX-License-Identifier: GPL-2.0-only */ |
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1 | 2 | /* |
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2 | 3 | * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com) |
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3 | | - * |
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4 | | - * This program is free software; you can redistribute it and/or modify |
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5 | | - * it under the terms of the GNU General Public License version 2 as |
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6 | | - * published by the Free Software Foundation. |
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7 | 4 | */ |
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8 | 5 | |
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9 | 6 | #ifndef __ASM_BARRIER_H |
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.. | .. |
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30 | 27 | #define rmb() asm volatile("dmb 1\n" : : : "memory") |
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31 | 28 | #define wmb() asm volatile("dmb 2\n" : : : "memory") |
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32 | 29 | |
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33 | | -#elif !defined(CONFIG_ARC_PLAT_EZNPS) /* CONFIG_ISA_ARCOMPACT */ |
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| 30 | +#else |
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34 | 31 | |
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35 | 32 | /* |
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36 | 33 | * ARCompact based cores (ARC700) only have SYNC instruction which is super |
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.. | .. |
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39 | 36 | */ |
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40 | 37 | |
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41 | 38 | #define mb() asm volatile("sync\n" : : : "memory") |
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42 | | - |
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43 | | -#else /* CONFIG_ARC_PLAT_EZNPS */ |
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44 | | - |
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45 | | -#include <plat/ctop.h> |
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46 | | - |
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47 | | -#define mb() asm volatile (".word %0" : : "i"(CTOP_INST_SCHD_RW) : "memory") |
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48 | | -#define rmb() asm volatile (".word %0" : : "i"(CTOP_INST_SCHD_RD) : "memory") |
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49 | 39 | |
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50 | 40 | #endif |
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51 | 41 | |
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