.. | .. |
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16 | 16 | #include <linux/sched.h> |
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17 | 17 | #include <linux/init.h> |
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18 | 18 | #include <linux/vmalloc.h> |
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19 | | -#include <linux/bootmem.h> |
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| 19 | +#include <linux/memblock.h> |
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20 | 20 | |
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21 | 21 | #include <asm/ptrace.h> |
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22 | 22 | #include <asm/smp.h> |
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23 | | -#include <asm/pgalloc.h> |
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24 | 23 | #include <asm/tlbflush.h> |
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25 | 24 | #include <asm/vga.h> |
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26 | 25 | |
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.. | .. |
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316 | 315 | * Window 1 is direct access 1GB at 2GB |
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317 | 316 | * Window 2 is scatter-gather 1GB at 3GB |
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318 | 317 | */ |
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319 | | - hose->sg_isa = iommu_arena_new(hose, 0x00800000, 0x00800000, 0); |
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| 318 | + hose->sg_isa = iommu_arena_new(hose, 0x00800000, 0x00800000, |
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| 319 | + SMP_CACHE_BYTES); |
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320 | 320 | hose->sg_isa->align_entry = 8; /* 64KB for ISA */ |
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321 | 321 | |
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322 | | - hose->sg_pci = iommu_arena_new(hose, 0xc0000000, 0x40000000, 0); |
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| 322 | + hose->sg_pci = iommu_arena_new(hose, 0xc0000000, 0x40000000, |
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| 323 | + SMP_CACHE_BYTES); |
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323 | 324 | hose->sg_pci->align_entry = 4; /* Titan caches 4 PTEs at a time */ |
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324 | 325 | |
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325 | 326 | port->wsba[0].csr = hose->sg_isa->dma_base | 3; |
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