forked from ~ljy/RK356X_SDK_RELEASE
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hc
2023-11-20 0d8657dd3056063fb115946b10157477b5c70451 
 kernel/drivers/video/rockchip/mpp/mpp_rkvenc2.c
....@@ -28,6 +28,8 @@
2828 #include <linux/nospec.h>
2929 #include <linux/workqueue.h>
3030 #include <linux/dma-iommu.h>
31
+#include <linux/mfd/syscon.h>
32
+#include <linux/rockchip/cpu.h>
3133 #include <soc/rockchip/pm_domains.h>
3234 #include <soc/rockchip/rockchip_ipa.h>
3335 #include <soc/rockchip/rockchip_opp_select.h>
....@@ -41,6 +43,7 @@
4143 
4244 #define	RKVENC_SESSION_MAX_BUFFERS		40
4345 #define RKVENC_MAX_CORE_NUM			4
46
+#define RKVENC_SCLR_DONE_STA			BIT(2)
4447 
4548 #define to_rkvenc_info(info)		\
4649 		container_of(info, struct rkvenc_hw_info, hw)
....@@ -187,6 +190,7 @@
187190 	dma_addr_t sram_iova;
188191 	u32 sram_enabled;
189192 	struct page *rcb_page;
193
+	struct regmap *grf;
190194 };
191195 
192196 
....@@ -699,6 +703,7 @@
699703 	struct rkvenc_dev *enc = to_rkvenc_dev(mpp);
700704 	struct rkvenc_task *task = to_rkvenc_task(mpp_task);
701705 	struct rkvenc_hw_info *hw = enc->hw_info;
706
+	u32 timing_en = mpp->srv->timing_en;
702707 
703708 	mpp_debug_enter();
704709 
....@@ -735,11 +740,20 @@
735740 		}
736741 	}
737742 
743
+	/* flush tlb before starting hardware */
744
+	mpp_iommu_flush_tlb(mpp->iommu_info);
745
+
738746 	/* init current task */
739747 	mpp->cur_task = mpp_task;
748
+
749
+	mpp_task_run_begin(mpp_task, timing_en, MPP_WORK_TIMEOUT_DELAY);
750
+
740751 	/* Flush the register before the start the device */
741752 	wmb();
753
+
742754 	mpp_write(mpp, enc->hw_info->enc_start_base, start_val);
755
+
756
+	mpp_task_run_end(mpp_task, timing_en);
743757 
744758 	mpp_debug_leave();
745759 
....@@ -793,6 +807,7 @@
793807 		if (mpp_debug_unlikely(DEBUG_DUMP_ERR_REG))
794808 			mpp_task_dump_hw_reg(mpp, mpp_task);
795809 	}
810
+
796811 	mpp_task_finish(mpp_task->session, mpp_task);
797812 
798813 	mpp_debug_leave();
....@@ -1031,6 +1046,10 @@
10311046 		enc->procfs = NULL;
10321047 		return -EIO;
10331048 	}
1049
+
1050
+	/* for common mpp_dev options */
1051
+	mpp_procfs_create_common(enc->procfs, mpp);
1052
+
10341053 	/* for debug */
10351054 	mpp_procfs_create_u32("aclk", 0644,
10361055 			      enc->procfs, &enc->aclk_info.debug_rate_hz);
....@@ -1063,7 +1082,7 @@
10631082 	struct rkvenc_dev *enc = to_rkvenc_dev(mpp);
10641083 	int ret = 0;
10651084 
1066
-	mpp->grf_info = &mpp->srv->grf_infos[MPP_DRIVER_RKVENC];
1085
+	mpp->grf_info = &mpp->srv->grf_infos[MPP_DRIVER_RKVENC2];
10671086 
10681087 	/* Get clock info from dtsi */
10691088 	ret = mpp_get_clk_info(mpp, &enc->aclk_info, "aclk_vcodec");
....@@ -1097,23 +1116,41 @@
10971116 	return 0;
10981117 }
10991118 
1100
-static int rkvenc_reset(struct mpp_dev *mpp)
1119
+static int rkvenc_soft_reset(struct mpp_dev *mpp)
11011120 {
11021121 	struct rkvenc_dev *enc = to_rkvenc_dev(mpp);
11031122 	struct rkvenc_hw_info *hw = enc->hw_info;
1104
-
1105
-	mpp_debug_enter();
1123
+	u32 rst_status = 0;
1124
+	int ret = 0;
11061125 
11071126 	/* safe reset */
11081127 	mpp_write(mpp, hw->int_mask_base, 0x3FF);
11091128 	mpp_write(mpp, hw->enc_clr_base, 0x1);
1110
-	udelay(5);
1129
+	ret = readl_relaxed_poll_timeout(mpp->reg_base + hw->int_sta_base,
1130
+					 rst_status,
1131
+					 rst_status & RKVENC_SCLR_DONE_STA,
1132
+					 0, 5);
11111133 	mpp_write(mpp, hw->int_clr_base, 0xffffffff);
11121134 	mpp_write(mpp, hw->int_sta_base, 0);
11131135 
1136
+	return ret;
1137
+
1138
+}
1139
+
1140
+static int rkvenc_reset(struct mpp_dev *mpp)
1141
+{
1142
+	struct rkvenc_dev *enc = to_rkvenc_dev(mpp);
1143
+	int ret = 0;
1144
+
1145
+	mpp_debug_enter();
1146
+
1147
+	/* safe reset first*/
1148
+	ret = rkvenc_soft_reset(mpp);
1149
+
11141150 	/* cru reset */
1115
-	if (enc->rst_a && enc->rst_h && enc->rst_core) {
1116
-		rockchip_pmu_idle_request(mpp->dev, true);
1151
+	if (ret && enc->rst_a && enc->rst_h && enc->rst_core) {
1152
+		mpp_err("soft reset timeout, use cru reset\n");
1153
+		mpp_pmu_idle_request(mpp, true);
11171154 		mpp_safe_reset(enc->rst_a);
11181155 		mpp_safe_reset(enc->rst_h);
11191156 		mpp_safe_reset(enc->rst_core);
....@@ -1121,7 +1158,7 @@
11211158 		mpp_safe_unreset(enc->rst_a);
11221159 		mpp_safe_unreset(enc->rst_h);
11231160 		mpp_safe_unreset(enc->rst_core);
1124
-		rockchip_pmu_idle_request(mpp->dev, false);
1161
+		mpp_pmu_idle_request(mpp, false);
11251162 	}
11261163 
11271164 	mpp_debug_leave();
....@@ -1338,6 +1375,7 @@
13381375 	}
13391376 	mpp->session_max_buffers = RKVENC_SESSION_MAX_BUFFERS;
13401377 	enc->hw_info = to_rkvenc_info(mpp->var->hw_info);
1378
+
13411379 	rkvenc_procfs_init(mpp);
13421380 	mpp_dev_register_srv(mpp, mpp->srv);
13431381 
....@@ -1416,12 +1454,44 @@
14161454 	dev_info(dev, "shutdown success\n");
14171455 }
14181456 
1457
+static int rkvenc_runtime_suspend(struct device *dev)
1458
+{
1459
+	struct mpp_dev *mpp = dev_get_drvdata(dev);
1460
+	struct mpp_grf_info *info = mpp->grf_info;
1461
+
1462
+	if (cpu_is_rk3528() && info && info->mem_offset)
1463
+		regmap_write(info->grf,
1464
+			     info->mem_offset,
1465
+			     info->val_mem_off);
1466
+
1467
+	return 0;
1468
+}
1469
+
1470
+static int rkvenc_runtime_resume(struct device *dev)
1471
+{
1472
+	struct mpp_dev *mpp = dev_get_drvdata(dev);
1473
+	struct mpp_grf_info *info = mpp->grf_info;
1474
+
1475
+	if (cpu_is_rk3528() && info && info->mem_offset)
1476
+		regmap_write(info->grf,
1477
+			     info->mem_offset,
1478
+			     info->val_mem_on);
1479
+
1480
+	return 0;
1481
+}
1482
+
1483
+static const struct dev_pm_ops rkvenc_pm_ops = {
1484
+	.runtime_suspend		= rkvenc_runtime_suspend,
1485
+	.runtime_resume			= rkvenc_runtime_resume,
1486
+};
1487
+
14191488 struct platform_driver rockchip_rkvenc2_driver = {
14201489 	.probe = rkvenc_probe,
14211490 	.remove = rkvenc_remove,
14221491 	.shutdown = rkvenc_shutdown,
14231492 	.driver = {
14241493 		.name = RKVENC_DRIVER_NAME,
1494
+		.pm = &rkvenc_pm_ops,
14251495 		.of_match_table = of_match_ptr(mpp_rkvenc_dt_match),
14261496 	},
14271497 };