enable lvds 1280x800

hc

2023-11-20 0d8657dd3056063fb115946b10157477b5c70451

 kernel/drivers/video/rockchip/mpp/mpp_rkvenc.c
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@@ -439,6 +439,7 @@
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 		int i;
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 		struct mpp_request *req;
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 		u32 reg_en = mpp_task->hw_info->reg_en;
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+		u32 timing_en = mpp->srv->timing_en;
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 		/*
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 		 * Tips: ensure osd plt clock is 0 before setting register,
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@@ -466,11 +467,20 @@
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 				rkvenc_write_req_backward(mpp, task->reg, s, e, reg_en);
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 			}
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 		}
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+
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+		/* flush tlb before starting hardware */
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+		mpp_iommu_flush_tlb(mpp->iommu_info);
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+
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 		/* init current task */
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 		mpp->cur_task = mpp_task;
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+
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+		mpp_task_run_begin(mpp_task, timing_en, MPP_WORK_TIMEOUT_DELAY);
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+
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 		/* Flush the register before the start the device */
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 		wmb();
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 		mpp_write(mpp, RKVENC_ENC_START_BASE, task->reg[reg_en]);
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+
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+		mpp_task_run_end(mpp_task, timing_en);
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 	} break;
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 	case RKVENC_MODE_LINKTABLE_FIX:
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 	case RKVENC_MODE_LINKTABLE_UPDATE:
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@@ -802,6 +812,10 @@
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 		enc->procfs = NULL;
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 		return -EIO;
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 	}
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+
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+	/* for common mpp_dev options */
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+	mpp_procfs_create_common(enc->procfs, mpp);
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+
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 	/* for debug */
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 	mpp_procfs_create_u32("aclk", 0644,
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 			      enc->procfs, &enc->aclk_info.debug_rate_hz);
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@@ -1264,7 +1278,7 @@
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 	mpp_write(mpp, RKVENC_INT_STATUS_BASE, 0);
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 	/* cru reset */
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 	if (enc->rst_a && enc->rst_h && enc->rst_core) {
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-		rockchip_pmu_idle_request(mpp->dev, true);
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+		mpp_pmu_idle_request(mpp, true);
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 		mpp_safe_reset(enc->rst_a);
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 		mpp_safe_reset(enc->rst_h);
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 		mpp_safe_reset(enc->rst_core);
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@@ -1272,7 +1286,7 @@
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 		mpp_safe_unreset(enc->rst_a);
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 		mpp_safe_unreset(enc->rst_h);
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 		mpp_safe_unreset(enc->rst_core);
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-		rockchip_pmu_idle_request(mpp->dev, false);
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+		mpp_pmu_idle_request(mpp, false);
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 	}
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 #ifdef CONFIG_PM_DEVFREQ
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 	if (enc->devfreq)