enable lvds 1280x800

hc

2023-11-20 0d8657dd3056063fb115946b10157477b5c70451

 kernel/drivers/video/rockchip/mpp/mpp_rkvdec2.c
..
..
@@ -17,8 +17,10 @@
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17
 
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 #include <linux/devfreq_cooling.h>
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 #include <soc/rockchip/rockchip_ipa.h>
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+#include <soc/rockchip/rockchip_dmc.h>
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 #include <soc/rockchip/rockchip_opp_select.h>
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 #include <soc/rockchip/rockchip_system_monitor.h>
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+#include <soc/rockchip/rockchip_iommu.h>
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24
 
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 #ifdef CONFIG_PM_DEVFREQ
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 #include "../../../devfreq/governor.h"
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@@ -304,6 +306,7 @@
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 static int rkvdec2_run(struct mpp_dev *mpp, struct mpp_task *mpp_task)
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 {
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 	struct rkvdec2_task *task = to_rkvdec2_task(mpp_task);
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+	u32 timing_en = mpp->srv->timing_en;
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 	u32 reg_en = mpp_task->hw_info->reg_en;
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 	/* set cache size */
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 	u32 reg = RKVDEC_CACHE_PERMIT_CACHEABLE_ACCESS |
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@@ -332,12 +335,20 @@
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 		e = s + req->size / sizeof(u32);
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 		mpp_write_req(mpp, task->reg, s, e, reg_en);
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 	}
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+
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+	/* flush tlb before starting hardware */
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+	mpp_iommu_flush_tlb(mpp->iommu_info);
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+
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 	/* init current task */
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 	mpp->cur_task = mpp_task;
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-	mpp_time_record(mpp_task);
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+
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+	mpp_task_run_begin(mpp_task, timing_en, MPP_WORK_TIMEOUT_DELAY);
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+
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 	/* Flush the register before the start the device */
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 	wmb();
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 	mpp_write(mpp, RKVDEC_REG_START_EN_BASE, task->reg[reg_en] | RKVDEC_START_EN);
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+
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+	mpp_task_run_end(mpp_task, timing_en);
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352
 
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 	mpp_debug_leave();
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..
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@@ -381,13 +392,15 @@
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 	u32 err_mask;
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 	struct rkvdec2_task *task = NULL;
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 	struct mpp_task *mpp_task = mpp->cur_task;
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+	struct rkvdec2_dev *dec = to_rkvdec2_dev(mpp);
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 	/* FIXME use a spin lock here */
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 	if (!mpp_task) {
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 		dev_err(mpp->dev, "no current task\n");
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 		return IRQ_HANDLED;
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 	}
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-	mpp_time_diff(mpp_task);
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+	mpp_task->hw_cycles = mpp_read(mpp, RKVDEC_PERF_WORKING_CNT);
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+	mpp_time_diff_with_hw_time(mpp_task, dec->core_clk_info.real_rate_hz);
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 	mpp->cur_task = NULL;
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 	task = to_rkvdec2_task(mpp_task);
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 	task->irq_status = mpp->irq_status;
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@@ -552,6 +565,16 @@
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 			}
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 		}
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 	} break;
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+	case MPP_CMD_SET_ERR_REF_HACK: {
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+		struct rkvdec2_dev *dec = to_rkvdec2_dev(session->mpp);
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+		u32 err_ref_hack_en = 0;
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+
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+		if (copy_from_user(&err_ref_hack_en, req->data, sizeof(u32))) {
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+			mpp_err("copy_from_user failed\n");
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+			return -EINVAL;
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+		}
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+		dec->err_ref_hack = err_ref_hack_en;
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+	} break;
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 	default: {
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 		mpp_err("unknown mpp ioctl cmd %x\n", req->cmd);
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 	} break;
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@@ -617,6 +640,10 @@
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 		dec->procfs = NULL;
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 		return -EIO;
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 	}
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+
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+	/* for common mpp_dev options */
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+	mpp_procfs_create_common(dec->procfs, mpp);
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+
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 	mpp_procfs_create_u32("aclk", 0644,
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 			      dec->procfs, &dec->aclk_info.debug_rate_hz);
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 	mpp_procfs_create_u32("clk_core", 0644,
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@@ -1067,17 +1094,41 @@
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 	return 0;
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 }
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+static int rkvdec2_soft_reset(struct mpp_dev *mpp)
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+{
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+	int ret = 0;
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+
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+	/*
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+	 * for rk3528 and rk3562
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+	 * use mmu reset instead of rkvdec soft reset
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+	 * rkvdec will reset together when rkvdec_mmu force reset
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+	 */
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+	ret = rockchip_iommu_force_reset(mpp->dev);
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+	if (ret)
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+		mpp_err("soft mmu reset fail, ret %d\n", ret);
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+	mpp_write(mpp, RKVDEC_REG_INT_EN, 0);
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+
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+	return ret;
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+
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+}
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+
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 static int rkvdec2_reset(struct mpp_dev *mpp)
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 {
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 	struct rkvdec2_dev *dec = to_rkvdec2_dev(mpp);
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+	int ret = 0;
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1119
 
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 	mpp_debug_enter();
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 #ifdef CONFIG_PM_DEVFREQ
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 	if (dec->devfreq)
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 		mutex_lock(&dec->devfreq->lock);
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 #endif
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-	if (dec->rst_a && dec->rst_h) {
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-		rockchip_pmu_idle_request(mpp->dev, true);
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+	/* safe reset first*/
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+	ret = rkvdec2_soft_reset(mpp);
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+
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+	/* cru reset */
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+	if (ret && dec->rst_a && dec->rst_h) {
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+		mpp_err("soft reset timeout, use cru reset\n");
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+		mpp_pmu_idle_request(mpp, true);
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 		mpp_safe_reset(dec->rst_niu_a);
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 		mpp_safe_reset(dec->rst_niu_h);
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 		mpp_safe_reset(dec->rst_a);
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@@ -1093,12 +1144,30 @@
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 		mpp_safe_unreset(dec->rst_core);
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 		mpp_safe_unreset(dec->rst_cabac);
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 		mpp_safe_unreset(dec->rst_hevc_cabac);
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-		rockchip_pmu_idle_request(mpp->dev, false);
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+		mpp_pmu_idle_request(mpp, false);
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 	}
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 #ifdef CONFIG_PM_DEVFREQ
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 	if (dec->devfreq)
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 		mutex_unlock(&dec->devfreq->lock);
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 #endif
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+	mpp_debug_leave();
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+
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+	return 0;
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+}
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+
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+static int rkvdec2_sip_reset(struct mpp_dev *mpp)
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+{
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+	mpp_debug_enter();
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+
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+	if (IS_REACHABLE(CONFIG_ROCKCHIP_SIP)) {
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+		/* sip reset */
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+		rockchip_dmcfreq_lock();
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+		sip_smc_vpu_reset(0, 0, 0);
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+		rockchip_dmcfreq_unlock();
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+	} else {
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+		rkvdec2_reset(mpp);
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+	}
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+
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 	mpp_debug_leave();
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 	return 0;
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@@ -1120,7 +1189,7 @@
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 	.clk_off = rkvdec2_clk_off,
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 	.get_freq = rkvdec2_get_freq,
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 	.set_freq = rkvdec2_set_freq,
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-	.reset = rkvdec2_reset,
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+	.reset = rkvdec2_sip_reset,
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 };
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 static struct mpp_dev_ops rkvdec_v2_dev_ops = {