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hc
2023-11-20 0d8657dd3056063fb115946b10157477b5c70451 
 kernel/drivers/thermal/rockchip_thermal.c
....@@ -230,6 +230,7 @@
230230 #define TSADCV2_AUTO_PERIOD_HT			0x6c
231231 #define TSADCV3_AUTO_PERIOD			0x154
232232 #define TSADCV3_AUTO_PERIOD_HT			0x158
233
+#define TSADCV3_Q_MAX				0x210
233234 
234235 #define TSADCV2_AUTO_EN				BIT(0)
235236 #define TSADCV2_AUTO_EN_MASK			BIT(16)
....@@ -240,6 +241,7 @@
240241 #define TSADCV2_AUTO_TSHUT_POLARITY_MASK	BIT(24)
241242 
242243 #define TSADCV3_AUTO_Q_SEL_EN			BIT(1)
244
+#define TSADCV3_AUTO_Q_SEL_EN_MASK		BIT(17)
243245 
244246 #define TSADCV2_INT_SRC_EN(chn)			BIT(chn)
245247 #define TSADCV2_INT_SRC_EN_MASK(chn)		BIT(16 + (chn))
....@@ -253,6 +255,7 @@
253255 #define TSADCV2_DATA_MASK			0xfff
254256 #define TSADCV3_DATA_MASK			0x3ff
255257 #define TSADCV4_DATA_MASK			0x1ff
258
+#define TSADCV5_DATA_MASK			0x7ff
256259 
257260 #define TSADCV2_HIGHT_INT_DEBOUNCE_COUNT	4
258261 #define TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT	4
....@@ -264,6 +267,9 @@
264267 #define TSADCV5_AUTO_PERIOD_HT_TIME		1622 /* 2.5ms */
265268 #define TSADCV6_AUTO_PERIOD_TIME		5000 /* 2.5ms */
266269 #define TSADCV6_AUTO_PERIOD_HT_TIME		5000 /* 2.5ms */
270
+#define TSADCV7_AUTO_PERIOD_TIME		3000 /* 2.5ms */
271
+#define TSADCV7_AUTO_PERIOD_HT_TIME		3000 /* 2.5ms */
272
+#define TSADCV3_Q_MAX_VAL			0x7ff /* 11bit 2047 */
267273 
268274 #define TSADCV2_USER_INTER_PD_SOC		0x340 /* 13 clocks */
269275 #define TSADCV5_USER_INTER_PD_SOC		0xfc0 /* 97us, at least 90us */
....@@ -278,6 +284,7 @@
278284 #define RK1808_BUS_GRF_SOC_CON0			0x0400
279285 
280286 #define RK3568_GRF_TSADC_CON			0x0600
287
+#define RK3528_GRF_TSADC_CON			0x40030
281288 #define RK3568_GRF_TSADC_ANA_REG0		(0x10001 << 0)
282289 #define RK3568_GRF_TSADC_ANA_REG1		(0x10001 << 1)
283290 #define RK3568_GRF_TSADC_ANA_REG2		(0x10001 << 2)
....@@ -299,9 +306,11 @@
299306 #define PX30S_TSADC_TDC_MODE			(0x10001 << 4)
300307 #define PX30S_TSADC_TRIM			(0xf0007 << 0)
301308 
302
-#define MIN_TEMP				(-40000)
309
+
310
+/* -40 to 125 is reliable, outside the range existed unreliability */
311
+#define MIN_TEMP				(-60000)
303312 #define LOWEST_TEMP				(-273000)
304
-#define MAX_TEMP				(125000)
313
+#define MAX_TEMP				(180000)
305314 #define MAX_ENV_TEMP				(85000)
306315 
307316 #define BASE					(1024)
....@@ -325,9 +334,9 @@
325334 	int temp;
326335 };
327336 
328
-
329337 static const struct tsadc_table rv1108_table[] = {
330
-	{0, -40000},
338
+	{0, MIN_TEMP},
339
+	{342, MIN_TEMP},
331340 	{374, -40000},
332341 	{382, -35000},
333342 	{389, -30000},
....@@ -362,11 +371,13 @@
362371 	{618, 115000},
363372 	{626, 120000},
364373 	{634, 125000},
365
-	{TSADCV2_DATA_MASK, 125000},
374
+	{722, MAX_TEMP},
375
+	{TSADCV2_DATA_MASK, MAX_TEMP},
366376 };
367377 
368378 static const struct tsadc_table rk1808_code_table[] = {
369
-	{0, -40000},
379
+	{0, MIN_TEMP},
380
+	{3423, MIN_TEMP},
370381 	{3455, -40000},
371382 	{3463, -35000},
372383 	{3471, -30000},
....@@ -401,11 +412,13 @@
401412 	{3709, 115000},
402413 	{3718, 120000},
403414 	{3726, 125000},
404
-	{TSADCV2_DATA_MASK, 125000},
415
+	{3820, MAX_TEMP},
416
+	{TSADCV2_DATA_MASK, MAX_TEMP},
405417 };
406418 
407419 static const struct tsadc_table rk3228_code_table[] = {
408
-	{0, -40000},
420
+	{0, MIN_TEMP},
421
+	{568, MIN_TEMP},
409422 	{588, -40000},
410423 	{593, -35000},
411424 	{598, -30000},
....@@ -440,11 +453,13 @@
440453 	{749, 115000},
441454 	{754, 120000},
442455 	{760, 125000},
443
-	{TSADCV2_DATA_MASK, 125000},
456
+	{821, MAX_TEMP},
457
+	{TSADCV2_DATA_MASK, MAX_TEMP},
444458 };
445459 
446460 static const struct tsadc_table rk3288_code_table[] = {
447
-	{TSADCV2_DATA_MASK, -40000},
461
+	{TSADCV2_DATA_MASK, MIN_TEMP},
462
+	{3833, MIN_TEMP},
448463 	{3800, -40000},
449464 	{3792, -35000},
450465 	{3783, -30000},
....@@ -479,11 +494,15 @@
479494 	{3452, 115000},
480495 	{3437, 120000},
481496 	{3421, 125000},
482
-	{0, 125000},
497
+	{3350, 145000},
498
+	{3270, 165000},
499
+	{3195, MAX_TEMP},
500
+	{0, MAX_TEMP},
483501 };
484502 
485503 static const struct tsadc_table rk3328_code_table[] = {
486
-	{0, -40000},
504
+	{0, MIN_TEMP},
505
+	{261, MIN_TEMP},
487506 	{296, -40000},
488507 	{304, -35000},
489508 	{313, -30000},
....@@ -517,11 +536,15 @@
517536 	{644, 115000},
518537 	{659, 120000},
519538 	{675, 125000},
520
-	{TSADCV2_DATA_MASK, 125000},
539
+	{745, 145000},
540
+	{825, 165000},
541
+	{900, MAX_TEMP},
542
+	{TSADCV2_DATA_MASK, MAX_TEMP},
521543 };
522544 
523545 static const struct tsadc_table rk3368_code_table[] = {
524
-	{0, -40000},
546
+	{0, MIN_TEMP},
547
+	{98, MIN_TEMP},
525548 	{106, -40000},
526549 	{108, -35000},
527550 	{110, -30000},
....@@ -556,11 +579,13 @@
556579 	{167, 115000},
557580 	{169, 120000},
558581 	{171, 125000},
559
-	{TSADCV3_DATA_MASK, 125000},
582
+	{193, MAX_TEMP},
583
+	{TSADCV3_DATA_MASK, MAX_TEMP},
560584 };
561585 
562586 static const struct tsadc_table rk3399_code_table[] = {
563
-	{0, -40000},
587
+	{0, MIN_TEMP},
588
+	{368, MIN_TEMP},
564589 	{402, -40000},
565590 	{410, -35000},
566591 	{419, -30000},
....@@ -595,11 +620,54 @@
595620 	{668, 115000},
596621 	{677, 120000},
597622 	{685, 125000},
598
-	{TSADCV3_DATA_MASK, 125000},
623
+	{782, MAX_TEMP},
624
+	{TSADCV3_DATA_MASK, MAX_TEMP},
625
+};
626
+
627
+static const struct tsadc_table rk3528_code_table[] = {
628
+	{0, MIN_TEMP},
629
+	{1386, MIN_TEMP},
630
+	{1419, -40000},
631
+	{1427, -35000},
632
+	{1435, -30000},
633
+	{1443, -25000},
634
+	{1452, -20000},
635
+	{1460, -15000},
636
+	{1468, -10000},
637
+	{1477, -5000},
638
+	{1486, 0},
639
+	{1494, 5000},
640
+	{1502, 10000},
641
+	{1510, 15000},
642
+	{1519, 20000},
643
+	{1527, 25000},
644
+	{1535, 30000},
645
+	{1544, 35000},
646
+	{1552, 40000},
647
+	{1561, 45000},
648
+	{1569, 50000},
649
+	{1578, 55000},
650
+	{1586, 60000},
651
+	{1594, 65000},
652
+	{1603, 70000},
653
+	{1612, 75000},
654
+	{1620, 80000},
655
+	{1628, 85000},
656
+	{1637, 90000},
657
+	{1646, 95000},
658
+	{1654, 100000},
659
+	{1662, 105000},
660
+	{1671, 110000},
661
+	{1679, 115000},
662
+	{1688, 120000},
663
+	{1696, 125000},
664
+	{1790, MAX_TEMP},
665
+	{TSADCV5_DATA_MASK, MAX_TEMP},
599666 };
600667 
601668 static const struct tsadc_table rk3568_code_table[] = {
602
-	{0, -40000},
669
+	{0, MIN_TEMP},
670
+	{1448, MIN_TEMP},
603671 	{1584, -40000},
604672 	{1620, -35000},
605673 	{1652, -30000},
....@@ -634,16 +702,19 @@
634702 	{2636, 115000},
635703 	{2672, 120000},
636704 	{2704, 125000},
637
-	{TSADCV2_DATA_MASK, 125000},
705
+	{3076, MAX_TEMP},
706
+	{TSADCV2_DATA_MASK, MAX_TEMP},
638707 };
639708 
640709 static const struct tsadc_table rk3588_code_table[] = {
641
-	{0, -40000},
710
+	{0, MIN_TEMP},
711
+	{194, MIN_TEMP},
642712 	{215, -40000},
643713 	{285, 25000},
644714 	{350, 85000},
645715 	{395, 125000},
646
-	{TSADCV4_DATA_MASK, 125000},
716
+	{455, MAX_TEMP},
717
+	{TSADCV4_DATA_MASK, MAX_TEMP},
647718 };
648719 
649720 static u32 rk_tsadcv2_temp_to_code(const struct chip_tsadc_table *table,
....@@ -968,6 +1039,37 @@
9681039 	if (!IS_ERR(grf)) {
9691040 		regmap_write(grf, PX30_GRF_SOC_CON0, PX30S_TSADC_TDC_MODE);
9701041 		regmap_write(grf, PX30_GRF_SOC_CON0, PX30S_TSADC_TRIM);
1042
+	}
1043
+}
1044
+
1045
+static void rk_tsadcv11_initialize(struct regmap *grf, void __iomem *regs,
1046
+				  enum tshut_polarity tshut_polarity)
1047
+{
1048
+	writel_relaxed(TSADCV7_AUTO_PERIOD_TIME, regs + TSADCV3_AUTO_PERIOD);
1049
+	writel_relaxed(TSADCV7_AUTO_PERIOD_HT_TIME,
1050
+		       regs + TSADCV3_AUTO_PERIOD_HT);
1051
+	writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT,
1052
+		       regs + TSADCV3_HIGHT_INT_DEBOUNCE);
1053
+	writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT,
1054
+		       regs + TSADCV3_HIGHT_TSHUT_DEBOUNCE);
1055
+	writel_relaxed(TSADCV3_Q_MAX_VAL, regs + TSADCV3_Q_MAX);
1056
+	writel_relaxed(TSADCV3_AUTO_Q_SEL_EN | TSADCV3_AUTO_Q_SEL_EN_MASK,
1057
+		       regs + TSADCV2_AUTO_CON);
1058
+	if (tshut_polarity == TSHUT_HIGH_ACTIVE)
1059
+		writel_relaxed(TSADCV2_AUTO_TSHUT_POLARITY_HIGH |
1060
+			       TSADCV2_AUTO_TSHUT_POLARITY_MASK,
1061
+			       regs + TSADCV2_AUTO_CON);
1062
+	else
1063
+		writel_relaxed(TSADCV2_AUTO_TSHUT_POLARITY_MASK,
1064
+			       regs + TSADCV2_AUTO_CON);
1065
+
1066
+	if (!IS_ERR(grf)) {
1067
+		regmap_write(grf, RK3528_GRF_TSADC_CON, RK3568_GRF_TSADC_TSEN);
1068
+		udelay(15);
1069
+		regmap_write(grf, RK3528_GRF_TSADC_CON, RK3568_GRF_TSADC_ANA_REG0);
1070
+		regmap_write(grf, RK3528_GRF_TSADC_CON, RK3568_GRF_TSADC_ANA_REG1);
1071
+		regmap_write(grf, RK3528_GRF_TSADC_CON, RK3568_GRF_TSADC_ANA_REG2);
1072
+		usleep_range(100, 200);
9711073 	}
9721074 }
9731075 
....@@ -1639,6 +1741,30 @@
16391741 	},
16401742 };
16411743 
1744
+static const struct rockchip_tsadc_chip rk3528_tsadc_data = {
1745
+	.chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
1746
+	.chn_num = 1, /* one channels for tsadc */
1747
+
1748
+	.tshut_mode = TSHUT_MODE_OTP, /* default TSHUT via GPIO give PMIC */
1749
+	.tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
1750
+	.tshut_temp = 95000,
1751
+
1752
+	.initialize = rk_tsadcv11_initialize,
1753
+	.irq_ack = rk_tsadcv4_irq_ack,
1754
+	.control = rk_tsadcv4_control,
1755
+	.get_temp = rk_tsadcv4_get_temp,
1756
+	.set_alarm_temp = rk_tsadcv3_alarm_temp,
1757
+	.set_tshut_temp = rk_tsadcv3_tshut_temp,
1758
+	.set_tshut_mode = rk_tsadcv4_tshut_mode,
1759
+
1760
+	.table = {
1761
+		.id = rk3528_code_table,
1762
+		.length = ARRAY_SIZE(rk3528_code_table),
1763
+		.data_mask = TSADCV2_DATA_MASK,
1764
+		.mode = ADC_INCREMENT,
1765
+	},
1766
+};
1767
+
16421768 static const struct rockchip_tsadc_chip rk3568_tsadc_data = {
16431769 	.chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
16441770 	.chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */
....@@ -1757,6 +1883,12 @@
17571883 		.data = (void *)&rk3399_tsadc_data,
17581884 	},
17591885 #endif
1886
+#ifdef CONFIG_CPU_RK3528
1887
+	{
1888
+		.compatible = "rockchip,rk3528-tsadc",
1889
+		.data = (void *)&rk3528_tsadc_data,
1890
+	},
1891
+#endif
17601892 #ifdef CONFIG_CPU_RK3568
17611893 	{
17621894 		.compatible = "rockchip,rk3568-tsadc",