| .. | .. |
|---|
| 586 | 586 | #define HDMI_I2CM_FS_SCL_LCNT_1_ADDR 0x7E11 |
|---|
| 587 | 587 | #define HDMI_I2CM_FS_SCL_LCNT_0_ADDR 0x7E12 |
|---|
| 588 | 588 | #define HDMI_I2CM_SDA_HOLD 0x7E13 |
|---|
| 589 | +#define HDMI_I2CM_SCDC_READ_UPDATE 0x7E14 |
|---|
| 590 | +#define HDMI_I2CM_READ_REQ_EN_MSK BIT(4) |
|---|
| 591 | +#define HDMI_I2CM_READ_REQ_EN_OFFSET 4 |
|---|
| 592 | +#define HDMI_I2CM_READ_UPDATE_MSK BIT(0) |
|---|
| 593 | +#define HDMI_I2CM_READ_UPDATE_OFFSET 0 |
|---|
| 594 | +#define HDMI_I2CM_I2CM_UPRD_VSYNC_EN_MSK BIT(5) |
|---|
| 595 | +#define HDMI_I2CM_I2CM_UPRD_VSYNC_EN_OFFSET 5 |
|---|
| 596 | +#define HDMI_I2CM_READ_BUFF0 0x7E20 |
|---|
| 597 | +#define HDMI_I2CM_SCDC_UPDATE0 0x7E30 |
|---|
| 598 | +#define HDMI_I2CM_SCDC_UPDATE1 0x7E31 |
|---|
| 589 | 599 | |
|---|
| 590 | 600 | enum { |
|---|
| 591 | 601 | /* PRODUCT_ID0 field values */ |
|---|
| .. | .. |
|---|
| 1152 | 1162 | HDMI_A_VIDPOLCFG_HSYNCPOL_ACTIVE_LOW = 0x0, |
|---|
| 1153 | 1163 | |
|---|
| 1154 | 1164 | /* I2CM_OPERATION field values */ |
|---|
| 1165 | + HDMI_I2CM_OPERATION_BUS_CLEAR = 0x20, |
|---|
| 1155 | 1166 | HDMI_I2CM_OPERATION_WRITE = 0x10, |
|---|
| 1167 | + HDMI_I2CM_OPERATION_READ8_EXT = 0x8, |
|---|
| 1168 | + HDMI_I2CM_OPERATION_READ8 = 0x4, |
|---|
| 1156 | 1169 | HDMI_I2CM_OPERATION_READ_EXT = 0x2, |
|---|
| 1157 | 1170 | HDMI_I2CM_OPERATION_READ = 0x1, |
|---|
| 1158 | 1171 | |
|---|