enable lvds 1280x800

hc

2023-11-20 0d8657dd3056063fb115946b10157477b5c70451

 kernel/drivers/char/tpm/tpm_tis.c
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@@ -54,6 +54,31 @@
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 	return container_of(data, struct tpm_tis_tcg_phy, priv);
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 }
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+#ifdef CONFIG_PREEMPT_RT_FULL
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+/*
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+ * Flushes previous write operations to chip so that a subsequent
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+ * ioread*()s won't stall a cpu.
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+ */
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+static inline void tpm_tis_flush(void __iomem *iobase)
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+{
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+	ioread8(iobase + TPM_ACCESS(0));
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+}
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+#else
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+#define tpm_tis_flush(iobase) do { } while (0)
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+#endif
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+
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+static inline void tpm_tis_iowrite8(u8 b, void __iomem *iobase, u32 addr)
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+{
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+	iowrite8(b, iobase + addr);
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+	tpm_tis_flush(iobase);
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+}
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+
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+static inline void tpm_tis_iowrite32(u32 b, void __iomem *iobase, u32 addr)
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+{
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+	iowrite32(b, iobase + addr);
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+	tpm_tis_flush(iobase);
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+}
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+
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 static int interrupts = -1;
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 module_param(interrupts, int, 0444);
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 MODULE_PARM_DESC(interrupts, "Enable interrupts");
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@@ -173,7 +198,7 @@
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 	struct tpm_tis_tcg_phy *phy = to_tpm_tis_tcg_phy(data);
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 	while (len--)
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-		iowrite8(*value++, phy->iobase + addr);
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+		tpm_tis_iowrite8(*value++, phy->iobase, addr);
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202
 
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 	return 0;
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 }
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@@ -200,7 +225,7 @@
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 {
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 	struct tpm_tis_tcg_phy *phy = to_tpm_tis_tcg_phy(data);
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-	iowrite32(value, phy->iobase + addr);
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+	tpm_tis_iowrite32(value, phy->iobase, addr);
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 	return 0;
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 }