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2024-05-10 093a6c67005148ae32a5c9e4553491b9f5c2457b 
 kernel/include/linux/qed/common_hsi.h
....@@ -1,33 +1,7 @@
1
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
12 /* QLogic qed NIC Driver
23  * Copyright (c) 2015-2016  QLogic Corporation
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- *
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- * This software is available to you under a choice of one of two
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- * licenses.  You may choose to be licensed under the terms of the GNU
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- * General Public License (GPL) Version 2, available from the file
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- * COPYING in the main directory of this source tree, or the
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- * OpenIB.org BSD license below:
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- *
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- *     Redistribution and use in source and binary forms, with or
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- *     without modification, are permitted provided that the following
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- *     conditions are met:
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- *
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- *      - Redistributions of source code must retain the above
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- *        copyright notice, this list of conditions and the following
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- *        disclaimer.
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- *
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- *      - Redistributions in binary form must reproduce the above
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- *        copyright notice, this list of conditions and the following
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- *        disclaimer in the documentation and /or other materials
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- *        provided with the distribution.
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- *
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- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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- * SOFTWARE.
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+ * Copyright (c) 2019-2020 Marvell International Ltd.
315  */
326 
337 #ifndef _COMMON_HSI_H
....@@ -76,7 +50,6 @@
7650 
7751 #define FW_ASSERT_GENERAL_ATTN_IDX		32
7852 
79
-#define MAX_PINNED_CCFC				32
8053 
8154 /* Queue Zone sizes in bytes */
8255 #define TSTORM_QZONE_SIZE	8
....@@ -105,12 +78,19 @@
10578 
10679 #define CORE_SPQE_PAGE_SIZE_BYTES	4096
10780 
108
-#define MAX_NUM_LL2_RX_QUEUES		48
109
-#define MAX_NUM_LL2_TX_STATS_COUNTERS	48
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+/* Number of LL2 RAM based queues */
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+#define MAX_NUM_LL2_RX_RAM_QUEUES 32
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+
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+/* Number of LL2 context based queues */
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+#define MAX_NUM_LL2_RX_CTX_QUEUES 208
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+#define MAX_NUM_LL2_RX_QUEUES \
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+	(MAX_NUM_LL2_RX_RAM_QUEUES + MAX_NUM_LL2_RX_CTX_QUEUES)
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+
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+#define MAX_NUM_LL2_TX_STATS_COUNTERS  48
11090 
11191 #define FW_MAJOR_VERSION	8
112
-#define FW_MINOR_VERSION        37
113
-#define FW_REVISION_VERSION     2
92
+#define FW_MINOR_VERSION	42
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+#define FW_REVISION_VERSION	2
11494 #define FW_ENGINEERING_VERSION	0
11595 
11696 /***********************/
....@@ -132,10 +112,10 @@
132112 #define MAX_NUM_VFS	(MAX_NUM_VFS_K2)
133113 
134114 #define MAX_NUM_FUNCTIONS_BB	(MAX_NUM_PFS_BB + MAX_NUM_VFS_BB)
135
-#define MAX_NUM_FUNCTIONS	(MAX_NUM_PFS + MAX_NUM_VFS)
136115 
137116 #define MAX_FUNCTION_NUMBER_BB	(MAX_NUM_PFS + MAX_NUM_VFS_BB)
138
-#define MAX_FUNCTION_NUMBER	(MAX_NUM_PFS + MAX_NUM_VFS)
117
+#define MAX_FUNCTION_NUMBER_K2  (MAX_NUM_PFS + MAX_NUM_VFS_K2)
118
+#define MAX_NUM_FUNCTIONS	(MAX_FUNCTION_NUMBER_K2)
139119 
140120 #define MAX_NUM_VPORTS_K2	(208)
141121 #define MAX_NUM_VPORTS_BB	(160)
....@@ -222,6 +202,7 @@
222202 #define DQ_XCM_TOE_TX_BD_PROD_CMD		DQ_XCM_AGG_VAL_SEL_WORD4
223203 #define DQ_XCM_TOE_MORE_TO_SEND_SEQ_CMD		DQ_XCM_AGG_VAL_SEL_REG3
224204 #define DQ_XCM_TOE_LOCAL_ADV_WND_SEQ_CMD	DQ_XCM_AGG_VAL_SEL_REG4
205
+#define DQ_XCM_ROCE_ACK_EDPM_DORQ_SEQ_CMD	DQ_XCM_AGG_VAL_SEL_WORD5
225206 
226207 /* UCM agg val selection (HW) */
227208 #define	DQ_UCM_AGG_VAL_SEL_WORD0	0
....@@ -340,6 +321,10 @@
340321 #define DQ_PWM_OFFSET_TCM_ROCE_RQ_PROD		(DQ_PWM_OFFSET_TCM16_BASE + 1)
341322 #define DQ_PWM_OFFSET_TCM_IWARP_RQ_PROD		(DQ_PWM_OFFSET_TCM16_BASE + 3)
342323 
324
+/* DQ_DEMS_AGG_VAL_BASE */
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+#define DQ_PWM_OFFSET_TCM_LL2_PROD_UPDATE \
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+	(DQ_PWM_OFFSET_TCM32_BASE + DQ_TCM_AGG_VAL_SEL_REG9 - 4)
327
+
343328 #define	DQ_REGION_SHIFT			(12)
344329 
345330 /* DPM */
....@@ -395,6 +380,7 @@
395380 
396381 /* Number of Protocol Indices per Status Block */
397382 #define PIS_PER_SB_E4	12
383
+#define MAX_PIS_PER_SB	PIS_PER_SB
398384 
399385 #define CAU_HC_STOPPED_STATE	3
400386 #define CAU_HC_DISABLE_STATE	4
....@@ -425,8 +411,6 @@
425411 #define IGU_MEM_PBA_MSIX_RESERVED_UPPER	0x03ff
426412 
427413 #define IGU_CMD_INT_ACK_BASE		0x0400
428
-#define IGU_CMD_INT_ACK_UPPER		(IGU_CMD_INT_ACK_BASE +	\
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-					 MAX_TOT_SB_PER_PATH - 1)
430414 #define IGU_CMD_INT_ACK_RESERVED_UPPER	0x05ff
431415 
432416 #define IGU_CMD_ATTN_BIT_UPD_UPPER	0x05f0
....@@ -439,8 +423,6 @@
439423 #define IGU_REG_SISR_MDPC_WOMASK_UPPER		0x05f6
440424 
441425 #define IGU_CMD_PROD_UPD_BASE			0x0600
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-#define IGU_CMD_PROD_UPD_UPPER			(IGU_CMD_PROD_UPD_BASE +\
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-						 MAX_TOT_SB_PER_PATH - 1)
444426 #define IGU_CMD_PROD_UPD_RESERVED_UPPER		0x07ff
445427 
446428 /*****************/
....@@ -652,8 +634,8 @@
652634 #define PBF_MAX_CMD_LINES	3328
653635 
654636 /* Number of BTB blocks. Each block is 256B. */
655
-#define BTB_MAX_BLOCKS		1440
656
-
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+#define BTB_MAX_BLOCKS_BB 1440
638
+#define BTB_MAX_BLOCKS_K2 1840
657639 /*****************/
658640 /* PRS CONSTANTS */
659641 /*****************/
....@@ -730,6 +712,8 @@
730712 	PROTOCOLID_PREROCE,
731713 	PROTOCOLID_COMMON,
732714 	PROTOCOLID_RESERVED1,
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+	PROTOCOLID_RDMA,
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+	PROTOCOLID_SCSI,
733717 	MAX_PROTOCOL_TYPE
734718 };
735719 
....@@ -748,6 +732,10 @@
748732 union rdma_eqe_data {
749733 	struct regpair async_handle;
750734 	struct rdma_eqe_destroy_qp rdma_destroy_qp_data;
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+};
736
+
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+struct tstorm_queue_zone {
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+	__le32 reserved[2];
751739 };
752740 
753741 /* Ustorm Queue Zone */
....@@ -872,8 +860,8 @@
872860 #define DB_L2_DPM_DATA_RESERVED0_SHIFT 27
873861 #define DB_L2_DPM_DATA_SGE_NUM_MASK	0x7
874862 #define DB_L2_DPM_DATA_SGE_NUM_SHIFT	28
875
-#define DB_L2_DPM_DATA_GFS_SRC_EN_MASK	0x1
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-#define DB_L2_DPM_DATA_GFS_SRC_EN_SHIFT	31
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+#define DB_L2_DPM_DATA_TGFS_SRC_EN_MASK  0x1
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+#define DB_L2_DPM_DATA_TGFS_SRC_EN_SHIFT 31
877865 };
878866 
879867 /* Structure for SGE in a DPM doorbell of type DPM_L2_BD */
....@@ -931,12 +919,12 @@
931919 #define DB_RDMA_DPM_PARAMS_WQE_SIZE_SHIFT		16
932920 #define DB_RDMA_DPM_PARAMS_RESERVED0_MASK		0x1
933921 #define DB_RDMA_DPM_PARAMS_RESERVED0_SHIFT		27
934
-#define DB_RDMA_DPM_PARAMS_COMPLETION_FLG_MASK		0x1
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-#define DB_RDMA_DPM_PARAMS_COMPLETION_FLG_SHIFT		28
922
+#define DB_RDMA_DPM_PARAMS_ACK_REQUEST_MASK		0x1
923
+#define DB_RDMA_DPM_PARAMS_ACK_REQUEST_SHIFT		28
936924 #define DB_RDMA_DPM_PARAMS_S_FLG_MASK			0x1
937925 #define DB_RDMA_DPM_PARAMS_S_FLG_SHIFT			29
938
-#define DB_RDMA_DPM_PARAMS_RESERVED1_MASK		0x1
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-#define DB_RDMA_DPM_PARAMS_RESERVED1_SHIFT		30
926
+#define DB_RDMA_DPM_PARAMS_COMPLETION_FLG_MASK		0x1
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+#define DB_RDMA_DPM_PARAMS_COMPLETION_FLG_SHIFT		30
940928 #define DB_RDMA_DPM_PARAMS_CONN_TYPE_IS_IWARP_MASK	0x1
941929 #define DB_RDMA_DPM_PARAMS_CONN_TYPE_IS_IWARP_SHIFT	31
942930 };