disable kernel build waring

hc

2024-05-10 093a6c67005148ae32a5c9e4553491b9f5c2457b

 kernel/include/linux/qcom-geni-se.h
..
..
@@ -1,10 +1,12 @@
1
-/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
1
+/* SPDX-License-Identifier: GPL-2.0 */
2
2
 /*
3
3
  * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
4
4
  */
5
5
 
6
6
 #ifndef _LINUX_QCOM_GENI_SE
7
7
 #define _LINUX_QCOM_GENI_SE
8
+
9
+#include <linux/interconnect.h>
8
10
 
9
11
 /* Transfer mode supported by GENI Serial Engines */
10
12
 enum geni_se_xfer_mode {
..
..
@@ -25,6 +27,17 @@
25
27
 struct geni_wrapper;
26
28
 struct clk;
27
29
 
30
+enum geni_icc_path_index {
31
+	GENI_TO_CORE,
32
+	CPU_TO_GENI,
33
+	GENI_TO_DDR
34
+};
35
+
36
+struct geni_icc_path {
37
+	struct icc_path *path;
38
+	unsigned int avg_bw;
39
+};
40
+
28
41
 /**
29
42
  * struct geni_se - GENI Serial Engine
30
43
  * @base:		Base Address of the Serial Engine's register block
..
..
@@ -33,6 +46,9 @@
33
46
  * @clk:		Handle to the core serial engine clock
34
47
  * @num_clk_levels:	Number of valid clock levels in clk_perf_tbl
35
48
  * @clk_perf_tbl:	Table of clock frequency input to serial engine clock
49
+ * @icc_paths:		Array of ICC paths for SE
50
+ * @opp_table:		Pointer to the OPP table
51
+ * @has_opp_table:	Specifies if the SE has an OPP table
36
52
  */
37
53
 struct geni_se {
38
54
 	void __iomem *base;
..
..
@@ -41,6 +57,9 @@
41
57
 	struct clk *clk;
42
58
 	unsigned int num_clk_levels;
43
59
 	unsigned long *clk_perf_tbl;
60
+	struct geni_icc_path icc_paths[3];
61
+	struct opp_table *opp_table;
62
+	bool has_opp_table;
44
63
 };
45
64
 
46
65
 /* Common SE registers */
..
..
@@ -225,18 +244,31 @@
225
244
 #define HW_VER_MINOR_SHFT		16
226
245
 #define HW_VER_STEP_MASK		GENMASK(15, 0)
227
246
 
247
+#define GENI_SE_VERSION_MAJOR(ver) ((ver & HW_VER_MAJOR_MASK) >> HW_VER_MAJOR_SHFT)
248
+#define GENI_SE_VERSION_MINOR(ver) ((ver & HW_VER_MINOR_MASK) >> HW_VER_MINOR_SHFT)
249
+#define GENI_SE_VERSION_STEP(ver) (ver & HW_VER_STEP_MASK)
250
+
251
+/* QUP SE VERSION value for major number 2 and minor number 5 */
252
+#define QUP_SE_VERSION_2_5                  0x20050000
253
+
254
+/*
255
+ * Define bandwidth thresholds that cause the underlying Core 2X interconnect
256
+ * clock to run at the named frequency. These baseline values are recommended
257
+ * by the hardware team, and are not dynamically scaled with GENI bandwidth
258
+ * beyond basic on/off.
259
+ */
260
+#define CORE_2X_19_2_MHZ		960
261
+#define CORE_2X_50_MHZ			2500
262
+#define CORE_2X_100_MHZ			5000
263
+#define CORE_2X_150_MHZ			7500
264
+#define CORE_2X_200_MHZ			10000
265
+#define CORE_2X_236_MHZ			16383
266
+
267
+#define GENI_DEFAULT_BW			Bps_to_icc(1000)
268
+
228
269
 #if IS_ENABLED(CONFIG_QCOM_GENI_SE)
229
270
 
230
271
 u32 geni_se_get_qup_hw_version(struct geni_se *se);
231
-
232
-#define geni_se_get_wrapper_version(se, major, minor, step) do { \
233
-	u32 ver; \
234
-\
235
-	ver = geni_se_get_qup_hw_version(se); \
236
-	major = (ver & HW_VER_MAJOR_MASK) >> HW_VER_MAJOR_SHFT; \
237
-	minor = (ver & HW_VER_MINOR_MASK) >> HW_VER_MINOR_SHFT; \
238
-	step = version & HW_VER_STEP_MASK; \
239
-} while (0)
240
272
 
241
273
 /**
242
274
  * geni_se_read_proto() - Read the protocol configured for a serial engine
..
..
@@ -267,7 +299,7 @@
267
299
 	u32 m_cmd;
268
300
 
269
301
 	m_cmd = (cmd << M_OPCODE_SHFT) | (params & M_PARAMS_MSK);
270
-	writel_relaxed(m_cmd, se->base + SE_GENI_M_CMD0);
302
+	writel(m_cmd, se->base + SE_GENI_M_CMD0);
271
303
 }
272
304
 
273
305
 /**
..
..
@@ -287,7 +319,7 @@
287
319
 	s_cmd &= ~(S_OPCODE_MSK | S_PARAMS_MSK);
288
320
 	s_cmd |= (cmd << S_OPCODE_SHFT);
289
321
 	s_cmd |= (params & S_PARAMS_MSK);
290
-	writel_relaxed(s_cmd, se->base + SE_GENI_S_CMD0);
322
+	writel(s_cmd, se->base + SE_GENI_S_CMD0);
291
323
 }
292
324
 
293
325
 /**
..
..
@@ -421,5 +453,14 @@
421
453
 void geni_se_tx_dma_unprep(struct geni_se *se, dma_addr_t iova, size_t len);
422
454
 
423
455
 void geni_se_rx_dma_unprep(struct geni_se *se, dma_addr_t iova, size_t len);
456
+
457
+int geni_icc_get(struct geni_se *se, const char *icc_ddr);
458
+
459
+int geni_icc_set_bw(struct geni_se *se);
460
+void geni_icc_set_tag(struct geni_se *se, u32 tag);
461
+
462
+int geni_icc_enable(struct geni_se *se);
463
+
464
+int geni_icc_disable(struct geni_se *se);
424
465
 #endif
425
466
 #endif