~hc/RK356X_SDK_RELEASE.git

..	..	@@ -1,20 +1,13 @@
	1	+/* SPDX-License-Identifier: GPL-2.0 */
1	2	/*
2	3	* Definitions for the NVM Express interface
3	4	* Copyright (c) 2011-2014, Intel Corporation.
4		- *
5		- * This program is free software; you can redistribute it and/or modify it
6		- * under the terms and conditions of the GNU General Public License,
7		- * version 2, as published by the Free Software Foundation.
8		- *
9		- * This program is distributed in the hope it will be useful, but WITHOUT
10		- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11		- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12		- * more details.
13	5	*/
14	6
15	7	#ifndef _LINUX_NVME_H
16	8	#define _LINUX_NVME_H
17	9
	10	+#include <linux/bits.h>
18	11	#include <linux/types.h>
19	12	#include <linux/uuid.h>
20	13
..	..	@@ -46,21 +39,28 @@
46	39	NVMF_ADDR_FAMILY_IP6 = 2, /* IP6 */
47	40	NVMF_ADDR_FAMILY_IB = 3, /* InfiniBand */
48	41	NVMF_ADDR_FAMILY_FC = 4, /* Fibre Channel */
	42	+ NVMF_ADDR_FAMILY_LOOP = 254, /* Reserved for host usage */
	43	+ NVMF_ADDR_FAMILY_MAX,
49	44	};
50	45
51	46	/* Transport Type codes for Discovery Log Page entry TRTYPE field */
52	47	enum {
53	48	NVMF_TRTYPE_RDMA = 1, /* RDMA */
54	49	NVMF_TRTYPE_FC = 2, /* Fibre Channel */
	50	+ NVMF_TRTYPE_TCP = 3, /* TCP/IP */
55	51	NVMF_TRTYPE_LOOP = 254, /* Reserved for host usage */
56	52	NVMF_TRTYPE_MAX,
57	53	};
58	54
59	55	/* Transport Requirements codes for Discovery Log Page entry TREQ field */
60	56	enum {
61		- NVMF_TREQ_NOT_SPECIFIED = 0, /* Not specified */
62		- NVMF_TREQ_REQUIRED = 1, /* Required */
63		- NVMF_TREQ_NOT_REQUIRED = 2, /* Not Required */
	57	+ NVMF_TREQ_NOT_SPECIFIED = 0, /* Not specified */
	58	+ NVMF_TREQ_REQUIRED = 1, /* Required */
	59	+ NVMF_TREQ_NOT_REQUIRED = 2, /* Not Required */
	60	+#define NVME_TREQ_SECURE_CHANNEL_MASK \
	61	+ (NVMF_TREQ_REQUIRED \| NVMF_TREQ_NOT_REQUIRED)
	62	+
	63	+ NVMF_TREQ_DISABLE_SQFLOW = (1 << 2), /* Supports SQ flow control disable */
64	64	};
65	65
66	66	/* RDMA QP Service Type codes for Discovery Log Page entry TSAS
..	..	@@ -110,8 +110,25 @@
110	110	NVME_REG_AQA = 0x0024, /* Admin Queue Attributes */
111	111	NVME_REG_ASQ = 0x0028, /* Admin SQ Base Address */
112	112	NVME_REG_ACQ = 0x0030, /* Admin CQ Base Address */
113		- NVME_REG_CMBLOC = 0x0038, /* Controller Memory Buffer Location */
	113	+ NVME_REG_CMBLOC = 0x0038, /* Controller Memory Buffer Location */
114	114	NVME_REG_CMBSZ = 0x003c, /* Controller Memory Buffer Size */
	115	+ NVME_REG_BPINFO = 0x0040, /* Boot Partition Information */
	116	+ NVME_REG_BPRSEL = 0x0044, /* Boot Partition Read Select */
	117	+ NVME_REG_BPMBL = 0x0048, /* Boot Partition Memory Buffer
	118	+ * Location
	119	+ */
	120	+ NVME_REG_CMBMSC = 0x0050, /* Controller Memory Buffer Memory
	121	+ * Space Control
	122	+ */
	123	+ NVME_REG_PMRCAP = 0x0e00, /* Persistent Memory Capabilities */
	124	+ NVME_REG_PMRCTL = 0x0e04, /* Persistent Memory Region Control */
	125	+ NVME_REG_PMRSTS = 0x0e08, /* Persistent Memory Region Status */
	126	+ NVME_REG_PMREBS = 0x0e0c, /* Persistent Memory Region Elasticity
	127	+ * Buffer Size
	128	+ */
	129	+ NVME_REG_PMRSWTP = 0x0e10, /* Persistent Memory Region Sustained
	130	+ * Write Throughput
	131	+ */
115	132	NVME_REG_DBS = 0x1000, /* SQ 0 Tail Doorbell */
116	133	};
117	134
..	..	@@ -119,8 +136,10 @@
119	136	#define NVME_CAP_TIMEOUT(cap) (((cap) >> 24) & 0xff)
120	137	#define NVME_CAP_STRIDE(cap) (((cap) >> 32) & 0xf)
121	138	#define NVME_CAP_NSSRC(cap) (((cap) >> 36) & 0x1)
	139	+#define NVME_CAP_CSS(cap) (((cap) >> 37) & 0xff)
122	140	#define NVME_CAP_MPSMIN(cap) (((cap) >> 48) & 0xf)
123	141	#define NVME_CAP_MPSMAX(cap) (((cap) >> 52) & 0xf)
	142	+#define NVME_CAP_CMBS(cap) (((cap) >> 57) & 0x1)
124	143
125	144	#define NVME_CMB_BIR(cmbloc) ((cmbloc) & 0x7)
126	145	#define NVME_CMB_OFST(cmbloc) (((cmbloc) >> 12) & 0xfffff)
..	..	@@ -143,12 +162,12 @@
143	162	* Submission and Completion Queue Entry Sizes for the NVM command set.
144	163	* (In bytes and specified as a power of two (2^n)).
145	164	*/
	165	+#define NVME_ADM_SQES 6
146	166	#define NVME_NVM_IOSQES 6
147	167	#define NVME_NVM_IOCQES 4
148	168
149	169	enum {
150	170	NVME_CC_ENABLE = 1 << 0,
151		- NVME_CC_CSS_NVM = 0 << 4,
152	171	NVME_CC_EN_SHIFT = 0,
153	172	NVME_CC_CSS_SHIFT = 4,
154	173	NVME_CC_MPS_SHIFT = 7,
..	..	@@ -156,6 +175,9 @@
156	175	NVME_CC_SHN_SHIFT = 14,
157	176	NVME_CC_IOSQES_SHIFT = 16,
158	177	NVME_CC_IOCQES_SHIFT = 20,
	178	+ NVME_CC_CSS_NVM = 0 << NVME_CC_CSS_SHIFT,
	179	+ NVME_CC_CSS_CSI = 6 << NVME_CC_CSS_SHIFT,
	180	+ NVME_CC_CSS_MASK = 7 << NVME_CC_CSS_SHIFT,
159	181	NVME_CC_AMS_RR = 0 << NVME_CC_AMS_SHIFT,
160	182	NVME_CC_AMS_WRRU = 1 << NVME_CC_AMS_SHIFT,
161	183	NVME_CC_AMS_VS = 7 << NVME_CC_AMS_SHIFT,
..	..	@@ -165,6 +187,8 @@
165	187	NVME_CC_SHN_MASK = 3 << NVME_CC_SHN_SHIFT,
166	188	NVME_CC_IOSQES = NVME_NVM_IOSQES << NVME_CC_IOSQES_SHIFT,
167	189	NVME_CC_IOCQES = NVME_NVM_IOCQES << NVME_CC_IOCQES_SHIFT,
	190	+ NVME_CAP_CSS_NVM = 1 << 0,
	191	+ NVME_CAP_CSS_CSI = 1 << 6,
168	192	NVME_CSTS_RDY = 1 << 0,
169	193	NVME_CSTS_CFS = 1 << 1,
170	194	NVME_CSTS_NSSRO = 1 << 4,
..	..	@@ -173,6 +197,8 @@
173	197	NVME_CSTS_SHST_OCCUR = 1 << 2,
174	198	NVME_CSTS_SHST_CMPLT = 2 << 2,
175	199	NVME_CSTS_SHST_MASK = 3 << 2,
	200	+ NVME_CMBMSC_CRE = 1 << 0,
	201	+ NVME_CMBMSC_CMSE = 1 << 1,
176	202	};
177	203
178	204	struct nvme_id_power_state {
..	..	@@ -198,6 +224,11 @@
198	224	NVME_PS_FLAGS_NON_OP_STATE = 1 << 1,
199	225	};
200	226
	227	+enum nvme_ctrl_attr {
	228	+ NVME_CTRL_ATTR_HID_128_BIT = (1 << 0),
	229	+ NVME_CTRL_ATTR_TBKAS = (1 << 6),
	230	+};
	231	+
201	232	struct nvme_id_ctrl {
202	233	__le16 vid;
203	234	__le16 ssvid;
..	..	@@ -214,7 +245,11 @@
214	245	__le32 rtd3e;
215	246	__le32 oaes;
216	247	__le32 ctratt;
217		- __u8 rsvd100[156];
	248	+ __u8 rsvd100[28];
	249	+ __le16 crdt1;
	250	+ __le16 crdt2;
	251	+ __le16 crdt3;
	252	+ __u8 rsvd134[122];
218	253	__le16 oacs;
219	254	__u8 acl;
220	255	__u8 aerl;
..	..	@@ -278,16 +313,27 @@
278	313	};
279	314
280	315	enum {
	316	+ NVME_CTRL_CMIC_MULTI_CTRL = 1 << 1,
	317	+ NVME_CTRL_CMIC_ANA = 1 << 3,
281	318	NVME_CTRL_ONCS_COMPARE = 1 << 0,
282	319	NVME_CTRL_ONCS_WRITE_UNCORRECTABLE = 1 << 1,
283	320	NVME_CTRL_ONCS_DSM = 1 << 2,
284	321	NVME_CTRL_ONCS_WRITE_ZEROES = 1 << 3,
	322	+ NVME_CTRL_ONCS_RESERVATIONS = 1 << 5,
285	323	NVME_CTRL_ONCS_TIMESTAMP = 1 << 6,
286	324	NVME_CTRL_VWC_PRESENT = 1 << 0,
287	325	NVME_CTRL_OACS_SEC_SUPP = 1 << 0,
288	326	NVME_CTRL_OACS_DIRECTIVES = 1 << 5,
289	327	NVME_CTRL_OACS_DBBUF_SUPP = 1 << 8,
290	328	NVME_CTRL_LPA_CMD_EFFECTS_LOG = 1 << 1,
	329	+ NVME_CTRL_CTRATT_128_ID = 1 << 0,
	330	+ NVME_CTRL_CTRATT_NON_OP_PSP = 1 << 1,
	331	+ NVME_CTRL_CTRATT_NVM_SETS = 1 << 2,
	332	+ NVME_CTRL_CTRATT_READ_RECV_LVLS = 1 << 3,
	333	+ NVME_CTRL_CTRATT_ENDURANCE_GROUPS = 1 << 4,
	334	+ NVME_CTRL_CTRATT_PREDICTABLE_LAT = 1 << 5,
	335	+ NVME_CTRL_CTRATT_NAMESPACE_GRANULARITY = 1 << 7,
	336	+ NVME_CTRL_CTRATT_UUID_LIST = 1 << 9,
291	337	};
292	338
293	339	struct nvme_lbaf {
..	..	@@ -309,7 +355,7 @@
309	355	__u8 nmic;
310	356	__u8 rescap;
311	357	__u8 fpi;
312		- __u8 rsvd33;
	358	+ __u8 dlfeat;
313	359	__le16 nawun;
314	360	__le16 nawupf;
315	361	__le16 nacwu;
..	..	@@ -318,11 +364,17 @@
318	364	__le16 nabspf;
319	365	__le16 noiob;
320	366	__u8 nvmcap[16];
321		- __u8 rsvd64[28];
	367	+ __le16 npwg;
	368	+ __le16 npwa;
	369	+ __le16 npdg;
	370	+ __le16 npda;
	371	+ __le16 nows;
	372	+ __u8 rsvd74[18];
322	373	__le32 anagrpid;
323	374	__u8 rsvd96[3];
324	375	__u8 nsattr;
325		- __u8 rsvd100[4];
	376	+ __le16 nvmsetid;
	377	+ __le16 endgid;
326	378	__u8 nguid[16];
327	379	__u8 eui64[8];
328	380	struct nvme_lbaf lbaf[16];
..	..	@@ -330,15 +382,49 @@
330	382	__u8 vs[3712];
331	383	};
332	384
	385	+struct nvme_zns_lbafe {
	386	+ __le64 zsze;
	387	+ __u8 zdes;
	388	+ __u8 rsvd9[7];
	389	+};
	390	+
	391	+struct nvme_id_ns_zns {
	392	+ __le16 zoc;
	393	+ __le16 ozcs;
	394	+ __le32 mar;
	395	+ __le32 mor;
	396	+ __le32 rrl;
	397	+ __le32 frl;
	398	+ __u8 rsvd20[2796];
	399	+ struct nvme_zns_lbafe lbafe[16];
	400	+ __u8 rsvd3072[768];
	401	+ __u8 vs[256];
	402	+};
	403	+
	404	+struct nvme_id_ctrl_zns {
	405	+ __u8 zasl;
	406	+ __u8 rsvd1[4095];
	407	+};
	408	+
333	409	enum {
334	410	NVME_ID_CNS_NS = 0x00,
335	411	NVME_ID_CNS_CTRL = 0x01,
336	412	NVME_ID_CNS_NS_ACTIVE_LIST = 0x02,
337	413	NVME_ID_CNS_NS_DESC_LIST = 0x03,
	414	+ NVME_ID_CNS_CS_NS = 0x05,
	415	+ NVME_ID_CNS_CS_CTRL = 0x06,
338	416	NVME_ID_CNS_NS_PRESENT_LIST = 0x10,
339	417	NVME_ID_CNS_NS_PRESENT = 0x11,
340	418	NVME_ID_CNS_CTRL_NS_LIST = 0x12,
341	419	NVME_ID_CNS_CTRL_LIST = 0x13,
	420	+ NVME_ID_CNS_SCNDRY_CTRL_LIST = 0x15,
	421	+ NVME_ID_CNS_NS_GRANULARITY = 0x16,
	422	+ NVME_ID_CNS_UUID_LIST = 0x17,
	423	+};
	424	+
	425	+enum {
	426	+ NVME_CSI_NVM = 0,
	427	+ NVME_CSI_ZNS = 2,
342	428	};
343	429
344	430	enum {
..	..	@@ -356,8 +442,12 @@
356	442
357	443	enum {
358	444	NVME_NS_FEAT_THIN = 1 << 0,
	445	+ NVME_NS_FEAT_ATOMICS = 1 << 1,
	446	+ NVME_NS_FEAT_IO_OPT = 1 << 4,
	447	+ NVME_NS_ATTR_RO = 1 << 0,
359	448	NVME_NS_FLBAS_LBA_MASK = 0xf,
360	449	NVME_NS_FLBAS_META_EXT = 0x10,
	450	+ NVME_NS_NMIC_SHARED = 1 << 0,
361	451	NVME_LBAF_RP_BEST = 0,
362	452	NVME_LBAF_RP_BETTER = 1,
363	453	NVME_LBAF_RP_GOOD = 2,
..	..	@@ -374,6 +464,12 @@
374	464	NVME_NS_DPS_PI_TYPE3 = 3,
375	465	};
376	466
	467	+/* Identify Namespace Metadata Capabilities (MC): */
	468	+enum {
	469	+ NVME_MC_EXTENDED_LBA = (1 << 0),
	470	+ NVME_MC_METADATA_PTR = (1 << 1),
	471	+};
	472	+
377	473	struct nvme_ns_id_desc {
378	474	__u8 nidt;
379	475	__u8 nidl;
..	..	@@ -383,11 +479,13 @@
383	479	#define NVME_NIDT_EUI64_LEN 8
384	480	#define NVME_NIDT_NGUID_LEN 16
385	481	#define NVME_NIDT_UUID_LEN 16
	482	+#define NVME_NIDT_CSI_LEN 1
386	483
387	484	enum {
388	485	NVME_NIDT_EUI64 = 0x01,
389	486	NVME_NIDT_NGUID = 0x02,
390	487	NVME_NIDT_UUID = 0x03,
	488	+ NVME_NIDT_CSI = 0x04,
391	489	};
392	490
393	491	struct nvme_smart_log {
..	..	@@ -396,7 +494,8 @@
396	494	__u8 avail_spare;
397	495	__u8 spare_thresh;
398	496	__u8 percent_used;
399		- __u8 rsvd6[26];
	497	+ __u8 endu_grp_crit_warn_sumry;
	498	+ __u8 rsvd7[25];
400	499	__u8 data_units_read[16];
401	500	__u8 data_units_written[16];
402	501	__u8 host_reads[16];
..	..	@@ -410,7 +509,11 @@
410	509	__le32 warning_temp_time;
411	510	__le32 critical_comp_time;
412	511	__le16 temp_sensor[8];
413		- __u8 rsvd216[296];
	512	+ __le32 thm_temp1_trans_count;
	513	+ __le32 thm_temp2_trans_count;
	514	+ __le32 thm_temp1_total_time;
	515	+ __le32 thm_temp2_total_time;
	516	+ __u8 rsvd232[280];
414	517	};
415	518
416	519	struct nvme_fw_slot_info_log {
..	..	@@ -426,7 +529,8 @@
426	529	NVME_CMD_EFFECTS_NCC = 1 << 2,
427	530	NVME_CMD_EFFECTS_NIC = 1 << 3,
428	531	NVME_CMD_EFFECTS_CCC = 1 << 4,
429		- NVME_CMD_EFFECTS_CSE_MASK = 3 << 16,
	532	+ NVME_CMD_EFFECTS_CSE_MASK = GENMASK(18, 16),
	533	+ NVME_CMD_EFFECTS_UUID_SEL = 1 << 19,
430	534	};
431	535
432	536	struct nvme_effects_log {
..	..	@@ -461,6 +565,27 @@
461	565	__le16 rsvd10[3];
462	566	};
463	567
	568	+struct nvme_zone_descriptor {
	569	+ __u8 zt;
	570	+ __u8 zs;
	571	+ __u8 za;
	572	+ __u8 rsvd3[5];
	573	+ __le64 zcap;
	574	+ __le64 zslba;
	575	+ __le64 wp;
	576	+ __u8 rsvd32[32];
	577	+};
	578	+
	579	+enum {
	580	+ NVME_ZONE_TYPE_SEQWRITE_REQ = 0x2,
	581	+};
	582	+
	583	+struct nvme_zone_report {
	584	+ __le64 nr_zones;
	585	+ __u8 resv8[56];
	586	+ struct nvme_zone_descriptor entries[];
	587	+};
	588	+
464	589	enum {
465	590	NVME_SMART_CRIT_SPARE = 1 << 0,
466	591	NVME_SMART_CRIT_TEMPERATURE = 1 << 1,
..	..	@@ -478,15 +603,28 @@
478	603	};
479	604
480	605	enum {
481		- NVME_AER_NOTICE_NS_CHANGED = 0x00,
482		- NVME_AER_NOTICE_FW_ACT_STARTING = 0x01,
483		- NVME_AER_NOTICE_ANA = 0x03,
	606	+ NVME_AER_ERROR_PERSIST_INT_ERR = 0x03,
484	607	};
485	608
486	609	enum {
487		- NVME_AEN_CFG_NS_ATTR = 1 << 8,
488		- NVME_AEN_CFG_FW_ACT = 1 << 9,
489		- NVME_AEN_CFG_ANA_CHANGE = 1 << 11,
	610	+ NVME_AER_NOTICE_NS_CHANGED = 0x00,
	611	+ NVME_AER_NOTICE_FW_ACT_STARTING = 0x01,
	612	+ NVME_AER_NOTICE_ANA = 0x03,
	613	+ NVME_AER_NOTICE_DISC_CHANGED = 0xf0,
	614	+};
	615	+
	616	+enum {
	617	+ NVME_AEN_BIT_NS_ATTR = 8,
	618	+ NVME_AEN_BIT_FW_ACT = 9,
	619	+ NVME_AEN_BIT_ANA_CHANGE = 11,
	620	+ NVME_AEN_BIT_DISC_CHANGE = 31,
	621	+};
	622	+
	623	+enum {
	624	+ NVME_AEN_CFG_NS_ATTR = 1 << NVME_AEN_BIT_NS_ATTR,
	625	+ NVME_AEN_CFG_FW_ACT = 1 << NVME_AEN_BIT_FW_ACT,
	626	+ NVME_AEN_CFG_ANA_CHANGE = 1 << NVME_AEN_BIT_ANA_CHANGE,
	627	+ NVME_AEN_CFG_DISC_CHANGE = 1 << NVME_AEN_BIT_DISC_CHANGE,
490	628	};
491	629
492	630	struct nvme_lba_range_type {
..	..	@@ -541,11 +679,31 @@
541	679	nvme_cmd_compare = 0x05,
542	680	nvme_cmd_write_zeroes = 0x08,
543	681	nvme_cmd_dsm = 0x09,
	682	+ nvme_cmd_verify = 0x0c,
544	683	nvme_cmd_resv_register = 0x0d,
545	684	nvme_cmd_resv_report = 0x0e,
546	685	nvme_cmd_resv_acquire = 0x11,
547	686	nvme_cmd_resv_release = 0x15,
	687	+ nvme_cmd_zone_mgmt_send = 0x79,
	688	+ nvme_cmd_zone_mgmt_recv = 0x7a,
	689	+ nvme_cmd_zone_append = 0x7d,
548	690	};
	691	+
	692	+#define nvme_opcode_name(opcode) { opcode, #opcode }
	693	+#define show_nvm_opcode_name(val) \
	694	+ __print_symbolic(val, \
	695	+ nvme_opcode_name(nvme_cmd_flush), \
	696	+ nvme_opcode_name(nvme_cmd_write), \
	697	+ nvme_opcode_name(nvme_cmd_read), \
	698	+ nvme_opcode_name(nvme_cmd_write_uncor), \
	699	+ nvme_opcode_name(nvme_cmd_compare), \
	700	+ nvme_opcode_name(nvme_cmd_write_zeroes), \
	701	+ nvme_opcode_name(nvme_cmd_dsm), \
	702	+ nvme_opcode_name(nvme_cmd_resv_register), \
	703	+ nvme_opcode_name(nvme_cmd_resv_report), \
	704	+ nvme_opcode_name(nvme_cmd_resv_acquire), \
	705	+ nvme_opcode_name(nvme_cmd_resv_release))
	706	+
549	707
550	708	/*
551	709	* Descriptor subtype - lower 4 bits of nvme_(keyed_)sgl_desc identifier
..	..	@@ -639,7 +797,12 @@
639	797	__le32 cdw2[2];
640	798	__le64 metadata;
641	799	union nvme_data_ptr dptr;
642		- __le32 cdw10[6];
	800	+ __le32 cdw10;
	801	+ __le32 cdw11;
	802	+ __le32 cdw12;
	803	+ __le32 cdw13;
	804	+ __le32 cdw14;
	805	+ __le32 cdw15;
643	806	};
644	807
645	808	struct nvme_rw_command {
..	..	@@ -662,6 +825,7 @@
662	825	enum {
663	826	NVME_RW_LR = 1 << 15,
664	827	NVME_RW_FUA = 1 << 14,
	828	+ NVME_RW_APPEND_PIREMAP = 1 << 9,
665	829	NVME_RW_DSM_FREQ_UNSPEC = 0,
666	830	NVME_RW_DSM_FREQ_TYPICAL = 1,
667	831	NVME_RW_DSM_FREQ_RARE = 2,
..	..	@@ -727,7 +891,60 @@
727	891	__le16 appmask;
728	892	};
729	893
	894	+enum nvme_zone_mgmt_action {
	895	+ NVME_ZONE_CLOSE = 0x1,
	896	+ NVME_ZONE_FINISH = 0x2,
	897	+ NVME_ZONE_OPEN = 0x3,
	898	+ NVME_ZONE_RESET = 0x4,
	899	+ NVME_ZONE_OFFLINE = 0x5,
	900	+ NVME_ZONE_SET_DESC_EXT = 0x10,
	901	+};
	902	+
	903	+struct nvme_zone_mgmt_send_cmd {
	904	+ __u8 opcode;
	905	+ __u8 flags;
	906	+ __u16 command_id;
	907	+ __le32 nsid;
	908	+ __le32 cdw2[2];
	909	+ __le64 metadata;
	910	+ union nvme_data_ptr dptr;
	911	+ __le64 slba;
	912	+ __le32 cdw12;
	913	+ __u8 zsa;
	914	+ __u8 select_all;
	915	+ __u8 rsvd13[2];
	916	+ __le32 cdw14[2];
	917	+};
	918	+
	919	+struct nvme_zone_mgmt_recv_cmd {
	920	+ __u8 opcode;
	921	+ __u8 flags;
	922	+ __u16 command_id;
	923	+ __le32 nsid;
	924	+ __le64 rsvd2[2];
	925	+ union nvme_data_ptr dptr;
	926	+ __le64 slba;
	927	+ __le32 numd;
	928	+ __u8 zra;
	929	+ __u8 zrasf;
	930	+ __u8 pr;
	931	+ __u8 rsvd13;
	932	+ __le32 cdw14[2];
	933	+};
	934	+
	935	+enum {
	936	+ NVME_ZRA_ZONE_REPORT = 0,
	937	+ NVME_ZRASF_ZONE_REPORT_ALL = 0,
	938	+ NVME_REPORT_ZONE_PARTIAL = 1,
	939	+};
	940	+
730	941	/* Features */
	942	+
	943	+enum {
	944	+ NVME_TEMP_THRESH_MASK = 0xffff,
	945	+ NVME_TEMP_THRESH_SELECT_SHIFT = 16,
	946	+ NVME_TEMP_THRESH_TYPE_UNDER = 0x100000,
	947	+};
731	948
732	949	struct nvme_feat_auto_pst {
733	950	__le64 entries[32];
..	..	@@ -736,6 +953,15 @@
736	953	enum {
737	954	NVME_HOST_MEM_ENABLE = (1 << 0),
738	955	NVME_HOST_MEM_RETURN = (1 << 1),
	956	+};
	957	+
	958	+struct nvme_feat_host_behavior {
	959	+ __u8 acre;
	960	+ __u8 resv1[511];
	961	+};
	962	+
	963	+enum {
	964	+ NVME_ENABLE_ACRE = 1,
739	965	};
740	966
741	967	/* Admin commands */
..	..	@@ -754,16 +980,49 @@
754	980	nvme_admin_ns_mgmt = 0x0d,
755	981	nvme_admin_activate_fw = 0x10,
756	982	nvme_admin_download_fw = 0x11,
	983	+ nvme_admin_dev_self_test = 0x14,
757	984	nvme_admin_ns_attach = 0x15,
758	985	nvme_admin_keep_alive = 0x18,
759	986	nvme_admin_directive_send = 0x19,
760	987	nvme_admin_directive_recv = 0x1a,
	988	+ nvme_admin_virtual_mgmt = 0x1c,
	989	+ nvme_admin_nvme_mi_send = 0x1d,
	990	+ nvme_admin_nvme_mi_recv = 0x1e,
761	991	nvme_admin_dbbuf = 0x7C,
762	992	nvme_admin_format_nvm = 0x80,
763	993	nvme_admin_security_send = 0x81,
764	994	nvme_admin_security_recv = 0x82,
765	995	nvme_admin_sanitize_nvm = 0x84,
	996	+ nvme_admin_get_lba_status = 0x86,
	997	+ nvme_admin_vendor_start = 0xC0,
766	998	};
	999	+
	1000	+#define nvme_admin_opcode_name(opcode) { opcode, #opcode }
	1001	+#define show_admin_opcode_name(val) \
	1002	+ __print_symbolic(val, \
	1003	+ nvme_admin_opcode_name(nvme_admin_delete_sq), \
	1004	+ nvme_admin_opcode_name(nvme_admin_create_sq), \
	1005	+ nvme_admin_opcode_name(nvme_admin_get_log_page), \
	1006	+ nvme_admin_opcode_name(nvme_admin_delete_cq), \
	1007	+ nvme_admin_opcode_name(nvme_admin_create_cq), \
	1008	+ nvme_admin_opcode_name(nvme_admin_identify), \
	1009	+ nvme_admin_opcode_name(nvme_admin_abort_cmd), \
	1010	+ nvme_admin_opcode_name(nvme_admin_set_features), \
	1011	+ nvme_admin_opcode_name(nvme_admin_get_features), \
	1012	+ nvme_admin_opcode_name(nvme_admin_async_event), \
	1013	+ nvme_admin_opcode_name(nvme_admin_ns_mgmt), \
	1014	+ nvme_admin_opcode_name(nvme_admin_activate_fw), \
	1015	+ nvme_admin_opcode_name(nvme_admin_download_fw), \
	1016	+ nvme_admin_opcode_name(nvme_admin_ns_attach), \
	1017	+ nvme_admin_opcode_name(nvme_admin_keep_alive), \
	1018	+ nvme_admin_opcode_name(nvme_admin_directive_send), \
	1019	+ nvme_admin_opcode_name(nvme_admin_directive_recv), \
	1020	+ nvme_admin_opcode_name(nvme_admin_dbbuf), \
	1021	+ nvme_admin_opcode_name(nvme_admin_format_nvm), \
	1022	+ nvme_admin_opcode_name(nvme_admin_security_send), \
	1023	+ nvme_admin_opcode_name(nvme_admin_security_recv), \
	1024	+ nvme_admin_opcode_name(nvme_admin_sanitize_nvm), \
	1025	+ nvme_admin_opcode_name(nvme_admin_get_lba_status))
767	1026
768	1027	enum {
769	1028	NVME_QUEUE_PHYS_CONTIG = (1 << 0),
..	..	@@ -792,16 +1051,24 @@
792	1051	NVME_FEAT_RRL = 0x12,
793	1052	NVME_FEAT_PLM_CONFIG = 0x13,
794	1053	NVME_FEAT_PLM_WINDOW = 0x14,
	1054	+ NVME_FEAT_HOST_BEHAVIOR = 0x16,
	1055	+ NVME_FEAT_SANITIZE = 0x17,
795	1056	NVME_FEAT_SW_PROGRESS = 0x80,
796	1057	NVME_FEAT_HOST_ID = 0x81,
797	1058	NVME_FEAT_RESV_MASK = 0x82,
798	1059	NVME_FEAT_RESV_PERSIST = 0x83,
799	1060	NVME_FEAT_WRITE_PROTECT = 0x84,
	1061	+ NVME_FEAT_VENDOR_START = 0xC0,
	1062	+ NVME_FEAT_VENDOR_END = 0xFF,
800	1063	NVME_LOG_ERROR = 0x01,
801	1064	NVME_LOG_SMART = 0x02,
802	1065	NVME_LOG_FW_SLOT = 0x03,
803	1066	NVME_LOG_CHANGED_NS = 0x04,
804	1067	NVME_LOG_CMD_EFFECTS = 0x05,
	1068	+ NVME_LOG_DEVICE_SELF_TEST = 0x06,
	1069	+ NVME_LOG_TELEMETRY_HOST = 0x07,
	1070	+ NVME_LOG_TELEMETRY_CTRL = 0x08,
	1071	+ NVME_LOG_ENDURANCE_GROUP = 0x09,
805	1072	NVME_LOG_ANA = 0x0c,
806	1073	NVME_LOG_DISC = 0x70,
807	1074	NVME_LOG_RESERVATION = 0x80,
..	..	@@ -830,7 +1097,9 @@
830	1097	__u8 cns;
831	1098	__u8 rsvd3;
832	1099	__le16 ctrlid;
833		- __u32 rsvd11[5];
	1100	+ __u8 rsvd11[3];
	1101	+ __u8 csi;
	1102	+ __u32 rsvd12[4];
834	1103	};
835	1104
836	1105	#define NVME_IDENTIFY_DATA_SIZE 4096
..	..	@@ -937,9 +1206,16 @@
937	1206	__le16 numdl;
938	1207	__le16 numdu;
939	1208	__u16 rsvd11;
940		- __le32 lpol;
941		- __le32 lpou;
942		- __u32 rsvd14[2];
	1209	+ union {
	1210	+ struct {
	1211	+ __le32 lpol;
	1212	+ __le32 lpou;
	1213	+ };
	1214	+ __le64 lpo;
	1215	+ };
	1216	+ __u8 rsvd14[3];
	1217	+ __u8 csi;
	1218	+ __u32 rsvd15;
943	1219	};
944	1220
945	1221	struct nvme_directive_cmd {
..	..	@@ -972,6 +1248,23 @@
972	1248	nvme_fabrics_type_connect = 0x01,
973	1249	nvme_fabrics_type_property_get = 0x04,
974	1250	};
	1251	+
	1252	+#define nvme_fabrics_type_name(type) { type, #type }
	1253	+#define show_fabrics_type_name(type) \
	1254	+ __print_symbolic(type, \
	1255	+ nvme_fabrics_type_name(nvme_fabrics_type_property_set), \
	1256	+ nvme_fabrics_type_name(nvme_fabrics_type_connect), \
	1257	+ nvme_fabrics_type_name(nvme_fabrics_type_property_get))
	1258	+
	1259	+/*
	1260	+ * If not fabrics command, fctype will be ignored.
	1261	+ */
	1262	+#define show_opcode_name(qid, opcode, fctype) \
	1263	+ ((opcode) == nvme_fabrics_command ? \
	1264	+ show_fabrics_type_name(fctype) : \
	1265	+ ((qid) ? \
	1266	+ show_nvm_opcode_name(opcode) : \
	1267	+ show_admin_opcode_name(opcode)))
975	1268
976	1269	struct nvmf_common_command {
977	1270	__u8 opcode;
..	..	@@ -1027,7 +1320,11 @@
1027	1320	__le64 numrec;
1028	1321	__le16 recfmt;
1029	1322	__u8 resv14[1006];
1030		- struct nvmf_disc_rsp_page_entry entries[0];
	1323	+ struct nvmf_disc_rsp_page_entry entries[];
	1324	+};
	1325	+
	1326	+enum {
	1327	+ NVME_CONNECT_DISABLE_SQFLOW = (1 << 2),
1031	1328	};
1032	1329
1033	1330	struct nvmf_connect_command {
..	..	@@ -1115,6 +1412,8 @@
1115	1412	struct nvme_format_cmd format;
1116	1413	struct nvme_dsm_cmd dsm;
1117	1414	struct nvme_write_zeroes_cmd write_zeroes;
	1415	+ struct nvme_zone_mgmt_send_cmd zms;
	1416	+ struct nvme_zone_mgmt_recv_cmd zmr;
1118	1417	struct nvme_abort_cmd abort;
1119	1418	struct nvme_get_log_page_command get_log_page;
1120	1419	struct nvmf_common_command fabrics;
..	..	@@ -1126,6 +1425,25 @@
1126	1425	};
1127	1426	};
1128	1427
	1428	+static inline bool nvme_is_fabrics(struct nvme_command *cmd)
	1429	+{
	1430	+ return cmd->common.opcode == nvme_fabrics_command;
	1431	+}
	1432	+
	1433	+struct nvme_error_slot {
	1434	+ __le64 error_count;
	1435	+ __le16 sqid;
	1436	+ __le16 cmdid;
	1437	+ __le16 status_field;
	1438	+ __le16 param_error_location;
	1439	+ __le64 lba;
	1440	+ __le32 nsid;
	1441	+ __u8 vs;
	1442	+ __u8 resv[3];
	1443	+ __le64 cs;
	1444	+ __u8 resv2[24];
	1445	+};
	1446	+
1129	1447	static inline bool nvme_is_write(struct nvme_command *cmd)
1130	1448	{
1131	1449	/*
..	..	@@ -1133,7 +1451,7 @@
1133	1451	*
1134	1452	* Why can't we simply have a Fabrics In and Fabrics out command?
1135	1453	*/
1136		- if (unlikely(cmd->common.opcode == nvme_fabrics_command))
	1454	+ if (unlikely(nvme_is_fabrics(cmd)))
1137	1455	return cmd->fabrics.fctype & 1;
1138	1456	return cmd->common.opcode & 1;
1139	1457	}
..	..	@@ -1164,7 +1482,11 @@
1164	1482	NVME_SC_SGL_INVALID_OFFSET = 0x16,
1165	1483	NVME_SC_SGL_INVALID_SUBTYPE = 0x17,
1166	1484
	1485	+ NVME_SC_SANITIZE_FAILED = 0x1C,
	1486	+ NVME_SC_SANITIZE_IN_PROGRESS = 0x1D,
	1487	+
1167	1488	NVME_SC_NS_WRITE_PROTECTED = 0x20,
	1489	+ NVME_SC_CMD_INTERRUPTED = 0x21,
1168	1490
1169	1491	NVME_SC_LBA_RANGE = 0x80,
1170	1492	NVME_SC_CAP_EXCEEDED = 0x81,
..	..	@@ -1193,15 +1515,17 @@
1193	1515	NVME_SC_FW_NEEDS_SUBSYS_RESET = 0x110,
1194	1516	NVME_SC_FW_NEEDS_RESET = 0x111,
1195	1517	NVME_SC_FW_NEEDS_MAX_TIME = 0x112,
1196		- NVME_SC_FW_ACIVATE_PROHIBITED = 0x113,
	1518	+ NVME_SC_FW_ACTIVATE_PROHIBITED = 0x113,
1197	1519	NVME_SC_OVERLAPPING_RANGE = 0x114,
1198		- NVME_SC_NS_INSUFFICENT_CAP = 0x115,
	1520	+ NVME_SC_NS_INSUFFICIENT_CAP = 0x115,
1199	1521	NVME_SC_NS_ID_UNAVAILABLE = 0x116,
1200	1522	NVME_SC_NS_ALREADY_ATTACHED = 0x118,
1201	1523	NVME_SC_NS_IS_PRIVATE = 0x119,
1202	1524	NVME_SC_NS_NOT_ATTACHED = 0x11a,
1203	1525	NVME_SC_THIN_PROV_NOT_SUPP = 0x11b,
1204	1526	NVME_SC_CTRL_LIST_INVALID = 0x11c,
	1527	+ NVME_SC_BP_WRITE_PROHIBITED = 0x11e,
	1528	+ NVME_SC_PMR_SAN_PROHIBITED = 0x123,
1205	1529
1206	1530	/*
1207	1531	* I/O Command Set Specific - NVM commands:
..	..	@@ -1224,6 +1548,18 @@
1224	1548	NVME_SC_AUTH_REQUIRED = 0x191,
1225	1549
1226	1550	/*
	1551	+ * I/O Command Set Specific - Zoned commands:
	1552	+ */
	1553	+ NVME_SC_ZONE_BOUNDARY_ERROR = 0x1b8,
	1554	+ NVME_SC_ZONE_FULL = 0x1b9,
	1555	+ NVME_SC_ZONE_READ_ONLY = 0x1ba,
	1556	+ NVME_SC_ZONE_OFFLINE = 0x1bb,
	1557	+ NVME_SC_ZONE_INVALID_WRITE = 0x1bc,
	1558	+ NVME_SC_ZONE_TOO_MANY_ACTIVE = 0x1bd,
	1559	+ NVME_SC_ZONE_TOO_MANY_OPEN = 0x1be,
	1560	+ NVME_SC_ZONE_INVALID_TRANSITION = 0x1bf,
	1561	+
	1562	+ /*
1227	1563	* Media and Data Integrity Errors:
1228	1564	*/
1229	1565	NVME_SC_WRITE_FAULT = 0x280,
..	..	@@ -1242,7 +1578,9 @@
1242	1578	NVME_SC_ANA_INACCESSIBLE = 0x302,
1243	1579	NVME_SC_ANA_TRANSITION = 0x303,
1244	1580	NVME_SC_HOST_PATH_ERROR = 0x370,
	1581	+ NVME_SC_HOST_ABORTED_CMD = 0x371,
1245	1582
	1583	+ NVME_SC_CRD = 0x1800,
1246	1584	NVME_SC_DNR = 0x4000,
1247	1585	};
1248	1586