disable kernel build waring

hc

2024-05-10 093a6c67005148ae32a5c9e4553491b9f5c2457b

 kernel/include/linux/mtd/rawnand.h
..
..
@@ -1,11 +1,8 @@
1
+/* SPDX-License-Identifier: GPL-2.0-only */
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2
 /*
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3
  *  Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org>
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4
  *                        Steven J. Hill <sjhill@realitydiluted.com>
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  *		          Thomas Gleixner <tglx@linutronix.de>
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License version 2 as
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- * published by the Free Software Foundation.
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6
  *
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7
  * Info:
11
8
  *	Contains standard defines and IDs for NAND flash devices
..
..
@@ -16,28 +13,18 @@
16
13
 #ifndef __LINUX_MTD_RAWNAND_H
17
14
 #define __LINUX_MTD_RAWNAND_H
18
15
 
19
-#include <linux/wait.h>
20
-#include <linux/spinlock.h>
21
16
 #include <linux/mtd/mtd.h>
17
+#include <linux/mtd/nand.h>
22
18
 #include <linux/mtd/flashchip.h>
23
19
 #include <linux/mtd/bbm.h>
20
+#include <linux/mtd/jedec.h>
21
+#include <linux/mtd/nand.h>
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+#include <linux/mtd/onfi.h>
23
+#include <linux/mutex.h>
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24
 #include <linux/of.h>
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25
 #include <linux/types.h>
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26
 
27
27
 struct nand_chip;
28
-struct nand_flash_dev;
29
-
30
-/* Scan and identify a NAND device */
31
-int nand_scan_with_ids(struct nand_chip *chip, int max_chips,
32
-		       struct nand_flash_dev *ids);
33
-
34
-static inline int nand_scan(struct nand_chip *chip, int max_chips)
35
-{
36
-	return nand_scan_with_ids(chip, max_chips, NULL);
37
-}
38
-
39
-/* Internal helper for board drivers which need to override command function */
40
-void nand_wait_ready(struct mtd_info *mtd);
41
28
 
42
29
 /* The maximum number of NAND chips in an array */
43
30
 #define NAND_MAX_CHIPS		8
..
..
@@ -95,25 +82,6 @@
95
82
 #define NAND_DATA_IFACE_CHECK_ONLY	-1
96
83
 
97
84
 /*
98
- * Constants for ECC_MODES
99
- */
100
-typedef enum {
101
-	NAND_ECC_NONE,
102
-	NAND_ECC_SOFT,
103
-	NAND_ECC_HW,
104
-	NAND_ECC_HW_SYNDROME,
105
-	NAND_ECC_HW_OOB_FIRST,
106
-	NAND_ECC_ON_DIE,
107
-} nand_ecc_modes_t;
108
-
109
-enum nand_ecc_algo {
110
-	NAND_ECC_UNKNOWN,
111
-	NAND_ECC_HAMMING,
112
-	NAND_ECC_BCH,
113
-	NAND_ECC_RS,
114
-};
115
-
116
-/*
117
85
  * Constants for Hardware ECC
118
86
  */
119
87
 /* Reset Hardware ECC for read */
..
..
@@ -130,342 +98,126 @@
130
98
  * pages and you want to rely on the default implementation.
131
99
  */
132
100
 #define NAND_ECC_GENERIC_ERASED_CHECK	BIT(0)
133
-#define NAND_ECC_MAXIMIZE		BIT(1)
134
-
135
-/* Bit mask for flags passed to do_nand_read_ecc */
136
-#define NAND_GET_DEVICE		0x80
137
-
138
101
 
139
102
 /*
140
103
  * Option constants for bizarre disfunctionality and real
141
104
  * features.
142
105
  */
106
+
143
107
 /* Buswidth is 16 bit */
144
-#define NAND_BUSWIDTH_16	0x00000002
108
+#define NAND_BUSWIDTH_16	BIT(1)
109
+
110
+/*
111
+ * When using software implementation of Hamming, we can specify which byte
112
+ * ordering should be used.
113
+ */
114
+#define NAND_ECC_SOFT_HAMMING_SM_ORDER	BIT(2)
115
+
145
116
 /* Chip has cache program function */
146
-#define NAND_CACHEPRG		0x00000008
117
+#define NAND_CACHEPRG		BIT(3)
118
+/* Options valid for Samsung large page devices */
119
+#define NAND_SAMSUNG_LP_OPTIONS NAND_CACHEPRG
120
+
147
121
 /*
148
122
  * Chip requires ready check on read (for auto-incremented sequential read).
149
123
  * True only for small page devices; large page devices do not support
150
124
  * autoincrement.
151
125
  */
152
-#define NAND_NEED_READRDY	0x00000100
126
+#define NAND_NEED_READRDY	BIT(8)
153
127
 
154
128
 /* Chip does not allow subpage writes */
155
-#define NAND_NO_SUBPAGE_WRITE	0x00000200
129
+#define NAND_NO_SUBPAGE_WRITE	BIT(9)
156
130
 
157
131
 /* Device is one of 'new' xD cards that expose fake nand command set */
158
-#define NAND_BROKEN_XD		0x00000400
132
+#define NAND_BROKEN_XD		BIT(10)
159
133
 
160
134
 /* Device behaves just like nand, but is readonly */
161
-#define NAND_ROM		0x00000800
135
+#define NAND_ROM		BIT(11)
162
136
 
163
137
 /* Device supports subpage reads */
164
-#define NAND_SUBPAGE_READ	0x00001000
138
+#define NAND_SUBPAGE_READ	BIT(12)
139
+/* Macros to identify the above */
140
+#define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ))
165
141
 
166
142
 /*
167
143
  * Some MLC NANDs need data scrambling to limit bitflips caused by repeated
168
144
  * patterns.
169
145
  */
170
-#define NAND_NEED_SCRAMBLING	0x00002000
146
+#define NAND_NEED_SCRAMBLING	BIT(13)
171
147
 
172
148
 /* Device needs 3rd row address cycle */
173
-#define NAND_ROW_ADDR_3		0x00004000
174
-
175
-/* Options valid for Samsung large page devices */
176
-#define NAND_SAMSUNG_LP_OPTIONS NAND_CACHEPRG
177
-
178
-/* Macros to identify the above */
179
-#define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG))
180
-#define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ))
181
-#define NAND_HAS_SUBPAGE_WRITE(chip) !((chip)->options & NAND_NO_SUBPAGE_WRITE)
149
+#define NAND_ROW_ADDR_3		BIT(14)
182
150
 
183
151
 /* Non chip related options */
184
152
 /* This option skips the bbt scan during initialization. */
185
-#define NAND_SKIP_BBTSCAN	0x00010000
153
+#define NAND_SKIP_BBTSCAN	BIT(16)
186
154
 /* Chip may not exist, so silence any errors in scan */
187
-#define NAND_SCAN_SILENT_NODEV	0x00040000
155
+#define NAND_SCAN_SILENT_NODEV	BIT(18)
156
+
188
157
 /*
189
158
  * Autodetect nand buswidth with readid/onfi.
190
159
  * This suppose the driver will configure the hardware in 8 bits mode
191
160
  * when calling nand_scan_ident, and update its configuration
192
161
  * before calling nand_scan_tail.
193
162
  */
194
-#define NAND_BUSWIDTH_AUTO      0x00080000
163
+#define NAND_BUSWIDTH_AUTO      BIT(19)
164
+
195
165
 /*
196
166
  * This option could be defined by controller drivers to protect against
197
167
  * kmap'ed, vmalloc'ed highmem buffers being passed from upper layers
198
168
  */
199
-#define NAND_USE_BOUNCE_BUFFER	0x00100000
169
+#define NAND_USES_DMA		BIT(20)
200
170
 
201
171
 /*
202
- * In case your controller is implementing ->cmd_ctrl() and is relying on the
203
- * default ->cmdfunc() implementation, you may want to let the core handle the
204
- * tCCS delay which is required when a column change (RNDIN or RNDOUT) is
205
- * requested.
172
+ * In case your controller is implementing ->legacy.cmd_ctrl() and is relying
173
+ * on the default ->cmdfunc() implementation, you may want to let the core
174
+ * handle the tCCS delay which is required when a column change (RNDIN or
175
+ * RNDOUT) is requested.
206
176
  * If your controller already takes care of this delay, you don't need to set
207
177
  * this flag.
208
178
  */
209
-#define NAND_WAIT_TCCS		0x00200000
179
+#define NAND_WAIT_TCCS		BIT(21)
210
180
 
211
181
 /*
212
182
  * Whether the NAND chip is a boot medium. Drivers might use this information
213
183
  * to select ECC algorithms supported by the boot ROM or similar restrictions.
214
184
  */
215
-#define NAND_IS_BOOT_MEDIUM	0x00400000
185
+#define NAND_IS_BOOT_MEDIUM	BIT(22)
216
186
 
217
-/* Options set by nand scan */
218
-/* Nand scan has allocated controller struct */
219
-#define NAND_CONTROLLER_ALLOC	0x80000000
187
+/*
188
+ * Do not try to tweak the timings at runtime. This is needed when the
189
+ * controller initializes the timings on itself or when it relies on
190
+ * configuration done by the bootloader.
191
+ */
192
+#define NAND_KEEP_TIMINGS	BIT(23)
193
+
194
+/*
195
+ * There are different places where the manufacturer stores the factory bad
196
+ * block markers.
197
+ *
198
+ * Position within the block: Each of these pages needs to be checked for a
199
+ * bad block marking pattern.
200
+ */
201
+#define NAND_BBM_FIRSTPAGE	BIT(24)
202
+#define NAND_BBM_SECONDPAGE	BIT(25)
203
+#define NAND_BBM_LASTPAGE	BIT(26)
204
+
205
+/*
206
+ * Some controllers with pipelined ECC engines override the BBM marker with
207
+ * data or ECC bytes, thus making bad block detection through bad block marker
208
+ * impossible. Let's flag those chips so the core knows it shouldn't check the
209
+ * BBM and consider all blocks good.
210
+ */
211
+#define NAND_NO_BBM_QUIRK	BIT(27)
220
212
 
221
213
 /* Cell info constants */
222
214
 #define NAND_CI_CHIPNR_MSK	0x03
223
215
 #define NAND_CI_CELLTYPE_MSK	0x0C
224
216
 #define NAND_CI_CELLTYPE_SHIFT	2
225
217
 
226
-/* Keep gcc happy */
227
-struct nand_chip;
228
-
229
-/* ONFI version bits */
230
-#define ONFI_VERSION_1_0		BIT(1)
231
-#define ONFI_VERSION_2_0		BIT(2)
232
-#define ONFI_VERSION_2_1		BIT(3)
233
-#define ONFI_VERSION_2_2		BIT(4)
234
-#define ONFI_VERSION_2_3		BIT(5)
235
-#define ONFI_VERSION_3_0		BIT(6)
236
-#define ONFI_VERSION_3_1		BIT(7)
237
-#define ONFI_VERSION_3_2		BIT(8)
238
-#define ONFI_VERSION_4_0		BIT(9)
239
-
240
-/* ONFI features */
241
-#define ONFI_FEATURE_16_BIT_BUS		(1 << 0)
242
-#define ONFI_FEATURE_EXT_PARAM_PAGE	(1 << 7)
243
-
244
-/* ONFI timing mode, used in both asynchronous and synchronous mode */
245
-#define ONFI_TIMING_MODE_0		(1 << 0)
246
-#define ONFI_TIMING_MODE_1		(1 << 1)
247
-#define ONFI_TIMING_MODE_2		(1 << 2)
248
-#define ONFI_TIMING_MODE_3		(1 << 3)
249
-#define ONFI_TIMING_MODE_4		(1 << 4)
250
-#define ONFI_TIMING_MODE_5		(1 << 5)
251
-#define ONFI_TIMING_MODE_UNKNOWN	(1 << 6)
252
-
253
-/* ONFI feature number/address */
254
-#define ONFI_FEATURE_NUMBER		256
255
-#define ONFI_FEATURE_ADDR_TIMING_MODE	0x1
256
-
257
-/* Vendor-specific feature address (Micron) */
258
-#define ONFI_FEATURE_ADDR_READ_RETRY	0x89
259
-#define ONFI_FEATURE_ON_DIE_ECC		0x90
260
-#define   ONFI_FEATURE_ON_DIE_ECC_EN	BIT(3)
261
-
262
-/* ONFI subfeature parameters length */
263
-#define ONFI_SUBFEATURE_PARAM_LEN	4
264
-
265
-/* ONFI optional commands SET/GET FEATURES supported? */
266
-#define ONFI_OPT_CMD_SET_GET_FEATURES	(1 << 2)
267
-
268
-struct nand_onfi_params {
269
-	/* rev info and features block */
270
-	/* 'O' 'N' 'F' 'I'  */
271
-	u8 sig[4];
272
-	__le16 revision;
273
-	__le16 features;
274
-	__le16 opt_cmd;
275
-	u8 reserved0[2];
276
-	__le16 ext_param_page_length; /* since ONFI 2.1 */
277
-	u8 num_of_param_pages;        /* since ONFI 2.1 */
278
-	u8 reserved1[17];
279
-
280
-	/* manufacturer information block */
281
-	char manufacturer[12];
282
-	char model[20];
283
-	u8 jedec_id;
284
-	__le16 date_code;
285
-	u8 reserved2[13];
286
-
287
-	/* memory organization block */
288
-	__le32 byte_per_page;
289
-	__le16 spare_bytes_per_page;
290
-	__le32 data_bytes_per_ppage;
291
-	__le16 spare_bytes_per_ppage;
292
-	__le32 pages_per_block;
293
-	__le32 blocks_per_lun;
294
-	u8 lun_count;
295
-	u8 addr_cycles;
296
-	u8 bits_per_cell;
297
-	__le16 bb_per_lun;
298
-	__le16 block_endurance;
299
-	u8 guaranteed_good_blocks;
300
-	__le16 guaranteed_block_endurance;
301
-	u8 programs_per_page;
302
-	u8 ppage_attr;
303
-	u8 ecc_bits;
304
-	u8 interleaved_bits;
305
-	u8 interleaved_ops;
306
-	u8 reserved3[13];
307
-
308
-	/* electrical parameter block */
309
-	u8 io_pin_capacitance_max;
310
-	__le16 async_timing_mode;
311
-	__le16 program_cache_timing_mode;
312
-	__le16 t_prog;
313
-	__le16 t_bers;
314
-	__le16 t_r;
315
-	__le16 t_ccs;
316
-	__le16 src_sync_timing_mode;
317
-	u8 src_ssync_features;
318
-	__le16 clk_pin_capacitance_typ;
319
-	__le16 io_pin_capacitance_typ;
320
-	__le16 input_pin_capacitance_typ;
321
-	u8 input_pin_capacitance_max;
322
-	u8 driver_strength_support;
323
-	__le16 t_int_r;
324
-	__le16 t_adl;
325
-	u8 reserved4[8];
326
-
327
-	/* vendor */
328
-	__le16 vendor_revision;
329
-	u8 vendor[88];
330
-
331
-	__le16 crc;
332
-} __packed;
333
-
334
-#define ONFI_CRC_BASE	0x4F4E
335
-
336
-/* Extended ECC information Block Definition (since ONFI 2.1) */
337
-struct onfi_ext_ecc_info {
338
-	u8 ecc_bits;
339
-	u8 codeword_size;
340
-	__le16 bb_per_lun;
341
-	__le16 block_endurance;
342
-	u8 reserved[2];
343
-} __packed;
344
-
345
-#define ONFI_SECTION_TYPE_0	0	/* Unused section. */
346
-#define ONFI_SECTION_TYPE_1	1	/* for additional sections. */
347
-#define ONFI_SECTION_TYPE_2	2	/* for ECC information. */
348
-struct onfi_ext_section {
349
-	u8 type;
350
-	u8 length;
351
-} __packed;
352
-
353
-#define ONFI_EXT_SECTION_MAX 8
354
-
355
-/* Extended Parameter Page Definition (since ONFI 2.1) */
356
-struct onfi_ext_param_page {
357
-	__le16 crc;
358
-	u8 sig[4];             /* 'E' 'P' 'P' 'S' */
359
-	u8 reserved0[10];
360
-	struct onfi_ext_section sections[ONFI_EXT_SECTION_MAX];
361
-
362
-	/*
363
-	 * The actual size of the Extended Parameter Page is in
364
-	 * @ext_param_page_length of nand_onfi_params{}.
365
-	 * The following are the variable length sections.
366
-	 * So we do not add any fields below. Please see the ONFI spec.
367
-	 */
368
-} __packed;
369
-
370
-struct jedec_ecc_info {
371
-	u8 ecc_bits;
372
-	u8 codeword_size;
373
-	__le16 bb_per_lun;
374
-	__le16 block_endurance;
375
-	u8 reserved[2];
376
-} __packed;
377
-
378
-/* JEDEC features */
379
-#define JEDEC_FEATURE_16_BIT_BUS	(1 << 0)
380
-
381
-struct nand_jedec_params {
382
-	/* rev info and features block */
383
-	/* 'J' 'E' 'S' 'D'  */
384
-	u8 sig[4];
385
-	__le16 revision;
386
-	__le16 features;
387
-	u8 opt_cmd[3];
388
-	__le16 sec_cmd;
389
-	u8 num_of_param_pages;
390
-	u8 reserved0[18];
391
-
392
-	/* manufacturer information block */
393
-	char manufacturer[12];
394
-	char model[20];
395
-	u8 jedec_id[6];
396
-	u8 reserved1[10];
397
-
398
-	/* memory organization block */
399
-	__le32 byte_per_page;
400
-	__le16 spare_bytes_per_page;
401
-	u8 reserved2[6];
402
-	__le32 pages_per_block;
403
-	__le32 blocks_per_lun;
404
-	u8 lun_count;
405
-	u8 addr_cycles;
406
-	u8 bits_per_cell;
407
-	u8 programs_per_page;
408
-	u8 multi_plane_addr;
409
-	u8 multi_plane_op_attr;
410
-	u8 reserved3[38];
411
-
412
-	/* electrical parameter block */
413
-	__le16 async_sdr_speed_grade;
414
-	__le16 toggle_ddr_speed_grade;
415
-	__le16 sync_ddr_speed_grade;
416
-	u8 async_sdr_features;
417
-	u8 toggle_ddr_features;
418
-	u8 sync_ddr_features;
419
-	__le16 t_prog;
420
-	__le16 t_bers;
421
-	__le16 t_r;
422
-	__le16 t_r_multi_plane;
423
-	__le16 t_ccs;
424
-	__le16 io_pin_capacitance_typ;
425
-	__le16 input_pin_capacitance_typ;
426
-	__le16 clk_pin_capacitance_typ;
427
-	u8 driver_strength_support;
428
-	__le16 t_adl;
429
-	u8 reserved4[36];
430
-
431
-	/* ECC and endurance block */
432
-	u8 guaranteed_good_blocks;
433
-	__le16 guaranteed_block_endurance;
434
-	struct jedec_ecc_info ecc_info[4];
435
-	u8 reserved5[29];
436
-
437
-	/* reserved */
438
-	u8 reserved6[148];
439
-
440
-	/* vendor */
441
-	__le16 vendor_rev_num;
442
-	u8 reserved7[88];
443
-
444
-	/* CRC for Parameter Page */
445
-	__le16 crc;
446
-} __packed;
447
-
448
-/**
449
- * struct onfi_params - ONFI specific parameters that will be reused
450
- * @version: ONFI version (BCD encoded), 0 if ONFI is not supported
451
- * @tPROG: Page program time
452
- * @tBERS: Block erase time
453
- * @tR: Page read time
454
- * @tCCS: Change column setup time
455
- * @async_timing_mode: Supported asynchronous timing mode
456
- * @vendor_revision: Vendor specific revision number
457
- * @vendor: Vendor specific data
458
- */
459
-struct onfi_params {
460
-	int version;
461
-	u16 tPROG;
462
-	u16 tBERS;
463
-	u16 tR;
464
-	u16 tCCS;
465
-	u16 async_timing_mode;
466
-	u16 vendor_revision;
467
-	u8 vendor[88];
468
-};
218
+/* Position within the OOB data of the page */
219
+#define NAND_BBM_POS_SMALL		5
220
+#define NAND_BBM_POS_LARGE		0
469
221
 
470
222
 /**
471
223
  * struct nand_parameters - NAND generic parameters from the parameter page
..
..
@@ -498,49 +250,6 @@
498
250
 	u8 data[NAND_MAX_ID_LEN];
499
251
 	int len;
500
252
 };
501
-
502
-/**
503
- * struct nand_controller_ops - Controller operations
504
- *
505
- * @attach_chip: this method is called after the NAND detection phase after
506
- *		 flash ID and MTD fields such as erase size, page size and OOB
507
- *		 size have been set up. ECC requirements are available if
508
- *		 provided by the NAND chip or device tree. Typically used to
509
- *		 choose the appropriate ECC configuration and allocate
510
- *		 associated resources.
511
- *		 This hook is optional.
512
- * @detach_chip: free all resources allocated/claimed in
513
- *		 nand_controller_ops->attach_chip().
514
- *		 This hook is optional.
515
- */
516
-struct nand_controller_ops {
517
-	int (*attach_chip)(struct nand_chip *chip);
518
-	void (*detach_chip)(struct nand_chip *chip);
519
-};
520
-
521
-/**
522
- * struct nand_controller - Structure used to describe a NAND controller
523
- *
524
- * @lock:               protection lock
525
- * @active:		the mtd device which holds the controller currently
526
- * @wq:			wait queue to sleep on if a NAND operation is in
527
- *			progress used instead of the per chip wait queue
528
- *			when a hw controller is available.
529
- * @ops:		NAND controller operations.
530
- */
531
-struct nand_controller {
532
-	spinlock_t lock;
533
-	struct nand_chip *active;
534
-	wait_queue_head_t wq;
535
-	const struct nand_controller_ops *ops;
536
-};
537
-
538
-static inline void nand_controller_init(struct nand_controller *nfc)
539
-{
540
-	nfc->active = NULL;
541
-	spin_lock_init(&nfc->lock);
542
-	init_waitqueue_head(&nfc->wq);
543
-}
544
253
 
545
254
 /**
546
255
  * struct nand_ecc_step_info - ECC step information of ECC engine
..
..
@@ -582,7 +291,8 @@
582
291
 
583
292
 /**
584
293
  * struct nand_ecc_ctrl - Control structure for ECC
585
- * @mode:	ECC mode
294
+ * @engine_type: ECC engine type
295
+ * @placement:	OOB bytes placement
586
296
  * @algo:	ECC algorithm
587
297
  * @steps:	number of ECC steps per page
588
298
  * @size:	data bytes per ECC step
..
..
@@ -610,7 +320,7 @@
610
320
  *			controller and always return contiguous in-band and
611
321
  *			out-of-band data even if they're not stored
612
322
  *			contiguously on the NAND chip (e.g.
613
- *			NAND_ECC_HW_SYNDROME interleaves in-band and
323
+ *			NAND_ECC_PLACEMENT_INTERLEAVED interleaves in-band and
614
324
  *			out-of-band data).
615
325
  * @write_page_raw:	function to write a raw page without ECC. This function
616
326
  *			should hide the specific layout used by the ECC
..
..
@@ -618,7 +328,7 @@
618
328
  *			in-band and out-of-band data. ECC controller is
619
329
  *			responsible for doing the appropriate transformations
620
330
  *			to adapt to its specific layout (e.g.
621
- *			NAND_ECC_HW_SYNDROME interleaves in-band and
331
+ *			NAND_ECC_PLACEMENT_INTERLEAVED interleaves in-band and
622
332
  *			out-of-band data).
623
333
  * @read_page:	function to read a page according to the ECC generator
624
334
  *		requirements; returns maximum number of bitflips corrected in
..
..
@@ -634,7 +344,8 @@
634
344
  * @write_oob:	function to write chip OOB data
635
345
  */
636
346
 struct nand_ecc_ctrl {
637
-	nand_ecc_modes_t mode;
347
+	enum nand_ecc_engine_type engine_type;
348
+	enum nand_ecc_placement placement;
638
349
 	enum nand_ecc_algo algo;
639
350
 	int steps;
640
351
 	int size;
..
..
@@ -647,31 +358,28 @@
647
358
 	void *priv;
648
359
 	u8 *calc_buf;
649
360
 	u8 *code_buf;
650
-	void (*hwctl)(struct mtd_info *mtd, int mode);
651
-	int (*calculate)(struct mtd_info *mtd, const uint8_t *dat,
652
-			uint8_t *ecc_code);
653
-	int (*correct)(struct mtd_info *mtd, uint8_t *dat, uint8_t *read_ecc,
654
-			uint8_t *calc_ecc);
655
-	int (*read_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
656
-			uint8_t *buf, int oob_required, int page);
657
-	int (*write_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
658
-			const uint8_t *buf, int oob_required, int page);
659
-	int (*read_page)(struct mtd_info *mtd, struct nand_chip *chip,
660
-			uint8_t *buf, int oob_required, int page);
661
-	int (*read_subpage)(struct mtd_info *mtd, struct nand_chip *chip,
662
-			uint32_t offs, uint32_t len, uint8_t *buf, int page);
663
-	int (*write_subpage)(struct mtd_info *mtd, struct nand_chip *chip,
664
-			uint32_t offset, uint32_t data_len,
665
-			const uint8_t *data_buf, int oob_required, int page);
666
-	int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
667
-			const uint8_t *buf, int oob_required, int page);
668
-	int (*write_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip,
669
-			int page);
670
-	int (*read_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip,
671
-			int page);
672
-	int (*read_oob)(struct mtd_info *mtd, struct nand_chip *chip, int page);
673
-	int (*write_oob)(struct mtd_info *mtd, struct nand_chip *chip,
674
-			int page);
361
+	void (*hwctl)(struct nand_chip *chip, int mode);
362
+	int (*calculate)(struct nand_chip *chip, const uint8_t *dat,
363
+			 uint8_t *ecc_code);
364
+	int (*correct)(struct nand_chip *chip, uint8_t *dat, uint8_t *read_ecc,
365
+		       uint8_t *calc_ecc);
366
+	int (*read_page_raw)(struct nand_chip *chip, uint8_t *buf,
367
+			     int oob_required, int page);
368
+	int (*write_page_raw)(struct nand_chip *chip, const uint8_t *buf,
369
+			      int oob_required, int page);
370
+	int (*read_page)(struct nand_chip *chip, uint8_t *buf,
371
+			 int oob_required, int page);
372
+	int (*read_subpage)(struct nand_chip *chip, uint32_t offs,
373
+			    uint32_t len, uint8_t *buf, int page);
374
+	int (*write_subpage)(struct nand_chip *chip, uint32_t offset,
375
+			     uint32_t data_len, const uint8_t *data_buf,
376
+			     int oob_required, int page);
377
+	int (*write_page)(struct nand_chip *chip, const uint8_t *buf,
378
+			  int oob_required, int page);
379
+	int (*write_oob_raw)(struct nand_chip *chip, int page);
380
+	int (*read_oob_raw)(struct nand_chip *chip, int page);
381
+	int (*read_oob)(struct nand_chip *chip, int page);
382
+	int (*write_oob)(struct nand_chip *chip, int page);
675
383
 };
676
384
 
677
385
 /**
..
..
@@ -767,56 +475,163 @@
767
475
 };
768
476
 
769
477
 /**
770
- * enum nand_data_interface_type - NAND interface timing type
771
- * @NAND_SDR_IFACE:	Single Data Rate interface
478
+ * struct nand_nvddr_timings - NV-DDR NAND chip timings
479
+ *
480
+ * This struct defines the timing requirements of a NV-DDR NAND data interface.
481
+ * These information can be found in every NAND datasheets and the timings
482
+ * meaning are described in the ONFI specifications:
483
+ * https://media-www.micron.com/-/media/client/onfi/specs/onfi_4_1_gold.pdf
484
+ * (chapter 4.18.2 NV-DDR)
485
+ *
486
+ * All these timings are expressed in picoseconds.
487
+ *
488
+ * @tBERS_max: Block erase time
489
+ * @tCCS_min: Change column setup time
490
+ * @tPROG_max: Page program time
491
+ * @tR_max: Page read time
492
+ * @tAC_min: Access window of DQ[7:0] from CLK
493
+ * @tAC_max: Access window of DQ[7:0] from CLK
494
+ * @tADL_min: ALE to data loading time
495
+ * @tCAD_min: Command, Address, Data delay
496
+ * @tCAH_min: Command/Address DQ hold time
497
+ * @tCALH_min: W/R_n, CLE and ALE hold time
498
+ * @tCALS_min: W/R_n, CLE and ALE setup time
499
+ * @tCAS_min: Command/address DQ setup time
500
+ * @tCEH_min: CE# high hold time
501
+ * @tCH_min:  CE# hold time
502
+ * @tCK_min: Average clock cycle time
503
+ * @tCS_min: CE# setup time
504
+ * @tDH_min: Data hold time
505
+ * @tDQSCK_min: Start of the access window of DQS from CLK
506
+ * @tDQSCK_max: End of the access window of DQS from CLK
507
+ * @tDQSD_min: Min W/R_n low to DQS/DQ driven by device
508
+ * @tDQSD_max: Max W/R_n low to DQS/DQ driven by device
509
+ * @tDQSHZ_max: W/R_n high to DQS/DQ tri-state by device
510
+ * @tDQSQ_max: DQS-DQ skew, DQS to last DQ valid, per access
511
+ * @tDS_min: Data setup time
512
+ * @tDSC_min: DQS cycle time
513
+ * @tFEAT_max: Busy time for Set Features and Get Features
514
+ * @tITC_max: Interface and Timing Mode Change time
515
+ * @tQHS_max: Data hold skew factor
516
+ * @tRHW_min: Data output cycle to command, address, or data input cycle
517
+ * @tRR_min: Ready to RE# low (data only)
518
+ * @tRST_max: Device reset time, measured from the falling edge of R/B# to the
519
+ *	      rising edge of R/B#.
520
+ * @tWB_max: WE# high to SR[6] low
521
+ * @tWHR_min: WE# high to RE# low
522
+ * @tWRCK_min: W/R_n low to data output cycle
523
+ * @tWW_min: WP# transition to WE# low
772
524
  */
773
-enum nand_data_interface_type {
774
-	NAND_SDR_IFACE,
525
+struct nand_nvddr_timings {
526
+	u64 tBERS_max;
527
+	u32 tCCS_min;
528
+	u64 tPROG_max;
529
+	u64 tR_max;
530
+	u32 tAC_min;
531
+	u32 tAC_max;
532
+	u32 tADL_min;
533
+	u32 tCAD_min;
534
+	u32 tCAH_min;
535
+	u32 tCALH_min;
536
+	u32 tCALS_min;
537
+	u32 tCAS_min;
538
+	u32 tCEH_min;
539
+	u32 tCH_min;
540
+	u32 tCK_min;
541
+	u32 tCS_min;
542
+	u32 tDH_min;
543
+	u32 tDQSCK_min;
544
+	u32 tDQSCK_max;
545
+	u32 tDQSD_min;
546
+	u32 tDQSD_max;
547
+	u32 tDQSHZ_max;
548
+	u32 tDQSQ_max;
549
+	u32 tDS_min;
550
+	u32 tDSC_min;
551
+	u32 tFEAT_max;
552
+	u32 tITC_max;
553
+	u32 tQHS_max;
554
+	u32 tRHW_min;
555
+	u32 tRR_min;
556
+	u32 tRST_max;
557
+	u32 tWB_max;
558
+	u32 tWHR_min;
559
+	u32 tWRCK_min;
560
+	u32 tWW_min;
775
561
 };
776
562
 
777
563
 /**
778
- * struct nand_data_interface - NAND interface timing
779
- * @type:	 type of the timing
780
- * @timings:	 The timing, type according to @type
781
- * @timings.sdr: Use it when @type is %NAND_SDR_IFACE.
564
+ * enum nand_interface_type - NAND interface type
565
+ * @NAND_SDR_IFACE:	Single Data Rate interface
566
+ * @NAND_NVDDR_IFACE:	Double Data Rate interface
782
567
  */
783
-struct nand_data_interface {
784
-	enum nand_data_interface_type type;
785
-	union {
786
-		struct nand_sdr_timings sdr;
568
+enum nand_interface_type {
569
+	NAND_SDR_IFACE,
570
+	NAND_NVDDR_IFACE,
571
+};
572
+
573
+/**
574
+ * struct nand_interface_config - NAND interface timing
575
+ * @type:	 type of the timing
576
+ * @timings:	 The timing information
577
+ * @timings.mode: Timing mode as defined in the specification
578
+ * @timings.sdr: Use it when @type is %NAND_SDR_IFACE.
579
+ * @timings.nvddr: Use it when @type is %NAND_NVDDR_IFACE.
580
+ */
581
+struct nand_interface_config {
582
+	enum nand_interface_type type;
583
+	struct nand_timings {
584
+		unsigned int mode;
585
+		union {
586
+			struct nand_sdr_timings sdr;
587
+			struct nand_nvddr_timings nvddr;
588
+		};
787
589
 	} timings;
788
590
 };
591
+
592
+/**
593
+ * nand_interface_is_sdr - get the interface type
594
+ * @conf:	The data interface
595
+ */
596
+static bool nand_interface_is_sdr(const struct nand_interface_config *conf)
597
+{
598
+	return conf->type == NAND_SDR_IFACE;
599
+}
600
+
601
+/**
602
+ * nand_interface_is_nvddr - get the interface type
603
+ * @conf:	The data interface
604
+ */
605
+static bool nand_interface_is_nvddr(const struct nand_interface_config *conf)
606
+{
607
+	return conf->type == NAND_NVDDR_IFACE;
608
+}
789
609
 
790
610
 /**
791
611
  * nand_get_sdr_timings - get SDR timing from data interface
792
612
  * @conf:	The data interface
793
613
  */
794
614
 static inline const struct nand_sdr_timings *
795
-nand_get_sdr_timings(const struct nand_data_interface *conf)
615
+nand_get_sdr_timings(const struct nand_interface_config *conf)
796
616
 {
797
-	if (conf->type != NAND_SDR_IFACE)
617
+	if (!nand_interface_is_sdr(conf))
798
618
 		return ERR_PTR(-EINVAL);
799
619
 
800
620
 	return &conf->timings.sdr;
801
621
 }
802
622
 
803
623
 /**
804
- * struct nand_manufacturer_ops - NAND Manufacturer operations
805
- * @detect: detect the NAND memory organization and capabilities
806
- * @init: initialize all vendor specific fields (like the ->read_retry()
807
- *	  implementation) if any.
808
- * @cleanup: the ->init() function may have allocated resources, ->cleanup()
809
- *	     is here to let vendor specific code release those resources.
810
- * @fixup_onfi_param_page: apply vendor specific fixups to the ONFI parameter
811
- *			   page. This is called after the checksum is verified.
624
+ * nand_get_nvddr_timings - get NV-DDR timing from data interface
625
+ * @conf:	The data interface
812
626
  */
813
-struct nand_manufacturer_ops {
814
-	void (*detect)(struct nand_chip *chip);
815
-	int (*init)(struct nand_chip *chip);
816
-	void (*cleanup)(struct nand_chip *chip);
817
-	void (*fixup_onfi_param_page)(struct nand_chip *chip,
818
-				      struct nand_onfi_params *p);
819
-};
627
+static inline const struct nand_nvddr_timings *
628
+nand_get_nvddr_timings(const struct nand_interface_config *conf)
629
+{
630
+	if (!nand_interface_is_nvddr(conf))
631
+		return ERR_PTR(-EINVAL);
632
+
633
+	return &conf->timings.nvddr;
634
+}
820
635
 
821
636
 /**
822
637
  * struct nand_op_cmd_instr - Definition of a command instruction
..
..
@@ -998,6 +813,7 @@
998
813
 
999
814
 /**
1000
815
  * struct nand_subop - a sub operation
816
+ * @cs: the CS line to select for this NAND sub-operation
1001
817
  * @instrs: array of instructions
1002
818
  * @ninstrs: length of the @instrs array
1003
819
  * @first_instr_start_off: offset to start from for the first instruction
..
..
@@ -1013,6 +829,7 @@
1013
829
  * controller driver.
1014
830
  */
1015
831
 struct nand_subop {
832
+	unsigned int cs;
1016
833
 	const struct nand_op_instr *instrs;
1017
834
 	unsigned int ninstrs;
1018
835
 	unsigned int first_instr_start_off;
..
..
@@ -1122,7 +939,7 @@
1122
939
 #define NAND_OP_PARSER_PATTERN(_exec, ...)							\
1123
940
 	{											\
1124
941
 		.exec = _exec,									\
1125
-		.elems = (struct nand_op_parser_pattern_elem[]) { __VA_ARGS__ },		\
942
+		.elems = (const struct nand_op_parser_pattern_elem[]) { __VA_ARGS__ },		\
1126
943
 		.nelems = sizeof((struct nand_op_parser_pattern_elem[]) { __VA_ARGS__ }) /	\
1127
944
 			  sizeof(struct nand_op_parser_pattern_elem),				\
1128
945
 	}
..
..
@@ -1148,25 +965,28 @@
1148
965
 
1149
966
 #define NAND_OP_PARSER(...)									\
1150
967
 	{											\
1151
-		.patterns = (struct nand_op_parser_pattern[]) { __VA_ARGS__ },			\
968
+		.patterns = (const struct nand_op_parser_pattern[]) { __VA_ARGS__ },		\
1152
969
 		.npatterns = sizeof((struct nand_op_parser_pattern[]) { __VA_ARGS__ }) /	\
1153
970
 			     sizeof(struct nand_op_parser_pattern),				\
1154
971
 	}
1155
972
 
1156
973
 /**
1157
974
  * struct nand_operation - NAND operation descriptor
975
+ * @cs: the CS line to select for this NAND operation
1158
976
  * @instrs: array of instructions to execute
1159
977
  * @ninstrs: length of the @instrs array
1160
978
  *
1161
979
  * The actual operation structure that will be passed to chip->exec_op().
1162
980
  */
1163
981
 struct nand_operation {
982
+	unsigned int cs;
1164
983
 	const struct nand_op_instr *instrs;
1165
984
 	unsigned int ninstrs;
1166
985
 };
1167
986
 
1168
-#define NAND_OPERATION(_instrs)					\
987
+#define NAND_OPERATION(_cs, _instrs)				\
1169
988
 	{							\
989
+		.cs = _cs,					\
1170
990
 		.instrs = _instrs,				\
1171
991
 		.ninstrs = ARRAY_SIZE(_instrs),			\
1172
992
 	}
..
..
@@ -1175,228 +995,286 @@
1175
995
 			   const struct nand_op_parser *parser,
1176
996
 			   const struct nand_operation *op, bool check_only);
1177
997
 
998
+static inline void nand_op_trace(const char *prefix,
999
+				 const struct nand_op_instr *instr)
1000
+{
1001
+#if IS_ENABLED(CONFIG_DYNAMIC_DEBUG) || defined(DEBUG)
1002
+	switch (instr->type) {
1003
+	case NAND_OP_CMD_INSTR:
1004
+		pr_debug("%sCMD      [0x%02x]\n", prefix,
1005
+			 instr->ctx.cmd.opcode);
1006
+		break;
1007
+	case NAND_OP_ADDR_INSTR:
1008
+		pr_debug("%sADDR     [%d cyc: %*ph]\n", prefix,
1009
+			 instr->ctx.addr.naddrs,
1010
+			 instr->ctx.addr.naddrs < 64 ?
1011
+			 instr->ctx.addr.naddrs : 64,
1012
+			 instr->ctx.addr.addrs);
1013
+		break;
1014
+	case NAND_OP_DATA_IN_INSTR:
1015
+		pr_debug("%sDATA_IN  [%d B%s]\n", prefix,
1016
+			 instr->ctx.data.len,
1017
+			 instr->ctx.data.force_8bit ?
1018
+			 ", force 8-bit" : "");
1019
+		break;
1020
+	case NAND_OP_DATA_OUT_INSTR:
1021
+		pr_debug("%sDATA_OUT [%d B%s]\n", prefix,
1022
+			 instr->ctx.data.len,
1023
+			 instr->ctx.data.force_8bit ?
1024
+			 ", force 8-bit" : "");
1025
+		break;
1026
+	case NAND_OP_WAITRDY_INSTR:
1027
+		pr_debug("%sWAITRDY  [max %d ms]\n", prefix,
1028
+			 instr->ctx.waitrdy.timeout_ms);
1029
+		break;
1030
+	}
1031
+#endif
1032
+}
1033
+
1178
1034
 /**
1179
- * struct nand_chip - NAND Private Flash Chip Data
1180
- * @mtd:		MTD device registered to the MTD framework
1181
- * @IO_ADDR_R:		[BOARDSPECIFIC] address to read the 8 I/O lines of the
1182
- *			flash device
1183
- * @IO_ADDR_W:		[BOARDSPECIFIC] address to write the 8 I/O lines of the
1184
- *			flash device.
1185
- * @read_byte:		[REPLACEABLE] read one byte from the chip
1186
- * @read_word:		[REPLACEABLE] read one word from the chip
1187
- * @write_byte:		[REPLACEABLE] write a single byte to the chip on the
1188
- *			low 8 I/O lines
1189
- * @write_buf:		[REPLACEABLE] write data from the buffer to the chip
1190
- * @read_buf:		[REPLACEABLE] read data from the chip into the buffer
1191
- * @select_chip:	[REPLACEABLE] select chip nr
1192
- * @block_bad:		[REPLACEABLE] check if a block is bad, using OOB markers
1193
- * @block_markbad:	[REPLACEABLE] mark a block bad
1194
- * @cmd_ctrl:		[BOARDSPECIFIC] hardwarespecific function for controlling
1195
- *			ALE/CLE/nCE. Also used to write command and address
1196
- * @dev_ready:		[BOARDSPECIFIC] hardwarespecific function for accessing
1197
- *			device ready/busy line. If set to NULL no access to
1198
- *			ready/busy is available and the ready/busy information
1199
- *			is read from the chip status register.
1200
- * @cmdfunc:		[REPLACEABLE] hardwarespecific function for writing
1201
- *			commands to the chip.
1202
- * @waitfunc:		[REPLACEABLE] hardwarespecific function for wait on
1203
- *			ready.
1204
- * @exec_op:		controller specific method to execute NAND operations.
1205
- *			This method replaces ->cmdfunc(),
1206
- *			->{read,write}_{buf,byte,word}(), ->dev_ready() and
1207
- *			->waifunc().
1208
- * @setup_read_retry:	[FLASHSPECIFIC] flash (vendor) specific function for
1209
- *			setting the read-retry mode. Mostly needed for MLC NAND.
1210
- * @ecc:		[BOARDSPECIFIC] ECC control structure
1211
- * @buf_align:		minimum buffer alignment required by a platform
1212
- * @dummy_controller:	dummy controller implementation for drivers that can
1213
- *			only control a single chip
1214
- * @erase:		[REPLACEABLE] erase function
1215
- * @chip_delay:		[BOARDSPECIFIC] chip dependent delay for transferring
1216
- *			data from array to read regs (tR).
1217
- * @state:		[INTERN] the current state of the NAND device
1218
- * @oob_poi:		"poison value buffer," used for laying out OOB data
1219
- *			before writing
1220
- * @page_shift:		[INTERN] number of address bits in a page (column
1221
- *			address bits).
1222
- * @phys_erase_shift:	[INTERN] number of address bits in a physical eraseblock
1223
- * @bbt_erase_shift:	[INTERN] number of address bits in a bbt entry
1224
- * @chip_shift:		[INTERN] number of address bits in one chip
1225
- * @options:		[BOARDSPECIFIC] various chip options. They can partly
1226
- *			be set to inform nand_scan about special functionality.
1227
- *			See the defines for further explanation.
1228
- * @bbt_options:	[INTERN] bad block specific options. All options used
1229
- *			here must come from bbm.h. By default, these options
1230
- *			will be copied to the appropriate nand_bbt_descr's.
1231
- * @badblockpos:	[INTERN] position of the bad block marker in the oob
1232
- *			area.
1233
- * @badblockbits:	[INTERN] minimum number of set bits in a good block's
1234
- *			bad block marker position; i.e., BBM == 11110111b is
1235
- *			not bad when badblockbits == 7
1236
- * @bits_per_cell:	[INTERN] number of bits per cell. i.e., 1 means SLC.
1237
- * @ecc_strength_ds:	[INTERN] ECC correctability from the datasheet.
1238
- *			Minimum amount of bit errors per @ecc_step_ds guaranteed
1239
- *			to be correctable. If unknown, set to zero.
1240
- * @ecc_step_ds:	[INTERN] ECC step required by the @ecc_strength_ds,
1241
- *			also from the datasheet. It is the recommended ECC step
1242
- *			size, if known; if unknown, set to zero.
1243
- * @onfi_timing_mode_default: [INTERN] default ONFI timing mode. This field is
1244
- *			      set to the actually used ONFI mode if the chip is
1245
- *			      ONFI compliant or deduced from the datasheet if
1246
- *			      the NAND chip is not ONFI compliant.
1247
- * @numchips:		[INTERN] number of physical chips
1248
- * @chipsize:		[INTERN] the size of one chip for multichip arrays
1249
- * @pagemask:		[INTERN] page number mask = number of (pages / chip) - 1
1250
- * @data_buf:		[INTERN] buffer for data, size is (page size + oobsize).
1251
- * @pagebuf:		[INTERN] holds the pagenumber which is currently in
1252
- *			data_buf.
1253
- * @pagebuf_bitflips:	[INTERN] holds the bitflip count for the page which is
1254
- *			currently in data_buf.
1255
- * @subpagesize:	[INTERN] holds the subpagesize
1256
- * @id:			[INTERN] holds NAND ID
1257
- * @parameters:		[INTERN] holds generic parameters under an easily
1258
- *			readable form.
1259
- * @max_bb_per_die:	[INTERN] the max number of bad blocks each die of a
1260
- *			this nand device will encounter their life times.
1261
- * @blocks_per_die:	[INTERN] The number of PEBs in a die
1262
- * @data_interface:	[INTERN] NAND interface timing information
1263
- * @read_retries:	[INTERN] the number of read retry modes supported
1264
- * @set_features:	[REPLACEABLE] set the NAND chip features
1265
- * @get_features:	[REPLACEABLE] get the NAND chip features
1266
- * @setup_data_interface: [OPTIONAL] setup the data interface and timing. If
1267
- *			  chipnr is set to %NAND_DATA_IFACE_CHECK_ONLY this
1268
- *			  means the configuration should not be applied but
1269
- *			  only checked.
1270
- * @bbt:		[INTERN] bad block table pointer
1271
- * @bbt_td:		[REPLACEABLE] bad block table descriptor for flash
1272
- *			lookup.
1273
- * @bbt_md:		[REPLACEABLE] bad block table mirror descriptor
1274
- * @badblock_pattern:	[REPLACEABLE] bad block scan pattern used for initial
1275
- *			bad block scan.
1276
- * @controller:		[REPLACEABLE] a pointer to a hardware controller
1277
- *			structure which is shared among multiple independent
1278
- *			devices.
1279
- * @priv:		[OPTIONAL] pointer to private chip data
1280
- * @manufacturer:	[INTERN] Contains manufacturer information
1281
- * @manufacturer.desc:	[INTERN] Contains manufacturer's description
1282
- * @manufacturer.priv:	[INTERN] Contains manufacturer private information
1035
+ * struct nand_controller_ops - Controller operations
1036
+ *
1037
+ * @attach_chip: this method is called after the NAND detection phase after
1038
+ *		 flash ID and MTD fields such as erase size, page size and OOB
1039
+ *		 size have been set up. ECC requirements are available if
1040
+ *		 provided by the NAND chip or device tree. Typically used to
1041
+ *		 choose the appropriate ECC configuration and allocate
1042
+ *		 associated resources.
1043
+ *		 This hook is optional.
1044
+ * @detach_chip: free all resources allocated/claimed in
1045
+ *		 nand_controller_ops->attach_chip().
1046
+ *		 This hook is optional.
1047
+ * @exec_op:	 controller specific method to execute NAND operations.
1048
+ *		 This method replaces chip->legacy.cmdfunc(),
1049
+ *		 chip->legacy.{read,write}_{buf,byte,word}(),
1050
+ *		 chip->legacy.dev_ready() and chip->legacy.waifunc().
1051
+ * @setup_interface: setup the data interface and timing. If chipnr is set to
1052
+ *		     %NAND_DATA_IFACE_CHECK_ONLY this means the configuration
1053
+ *		     should not be applied but only checked.
1054
+ *		     This hook is optional.
1283
1055
  */
1284
-
1285
-struct nand_chip {
1286
-	struct mtd_info mtd;
1287
-	void __iomem *IO_ADDR_R;
1288
-	void __iomem *IO_ADDR_W;
1289
-
1290
-	uint8_t (*read_byte)(struct mtd_info *mtd);
1291
-	u16 (*read_word)(struct mtd_info *mtd);
1292
-	void (*write_byte)(struct mtd_info *mtd, uint8_t byte);
1293
-	void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
1294
-	void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
1295
-	void (*select_chip)(struct mtd_info *mtd, int chip);
1296
-	int (*block_bad)(struct mtd_info *mtd, loff_t ofs);
1297
-	int (*block_markbad)(struct mtd_info *mtd, loff_t ofs);
1298
-	void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
1299
-	int (*dev_ready)(struct mtd_info *mtd);
1300
-	void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column,
1301
-			int page_addr);
1302
-	int(*waitfunc)(struct mtd_info *mtd, struct nand_chip *this);
1056
+struct nand_controller_ops {
1057
+	int (*attach_chip)(struct nand_chip *chip);
1058
+	void (*detach_chip)(struct nand_chip *chip);
1303
1059
 	int (*exec_op)(struct nand_chip *chip,
1304
1060
 		       const struct nand_operation *op,
1305
1061
 		       bool check_only);
1306
-	int (*erase)(struct mtd_info *mtd, int page);
1307
-	int (*set_features)(struct mtd_info *mtd, struct nand_chip *chip,
1308
-			    int feature_addr, uint8_t *subfeature_para);
1309
-	int (*get_features)(struct mtd_info *mtd, struct nand_chip *chip,
1310
-			    int feature_addr, uint8_t *subfeature_para);
1311
-	int (*setup_read_retry)(struct mtd_info *mtd, int retry_mode);
1312
-	int (*setup_data_interface)(struct mtd_info *mtd, int chipnr,
1313
-				    const struct nand_data_interface *conf);
1314
-
1315
-	int chip_delay;
1316
-	unsigned int options;
1317
-	unsigned int bbt_options;
1318
-
1319
-	int page_shift;
1320
-	int phys_erase_shift;
1321
-	int bbt_erase_shift;
1322
-	int chip_shift;
1323
-	int numchips;
1324
-	uint64_t chipsize;
1325
-	int pagemask;
1326
-	u8 *data_buf;
1327
-	int pagebuf;
1328
-	unsigned int pagebuf_bitflips;
1329
-	int subpagesize;
1330
-	uint8_t bits_per_cell;
1331
-	uint16_t ecc_strength_ds;
1332
-	uint16_t ecc_step_ds;
1333
-	int onfi_timing_mode_default;
1334
-	int badblockpos;
1335
-	int badblockbits;
1336
-
1337
-	struct nand_id id;
1338
-	struct nand_parameters parameters;
1339
-	u16 max_bb_per_die;
1340
-	u32 blocks_per_die;
1341
-
1342
-	struct nand_data_interface data_interface;
1343
-
1344
-	int read_retries;
1345
-
1346
-	flstate_t state;
1347
-
1348
-	uint8_t *oob_poi;
1349
-	struct nand_controller *controller;
1350
-
1351
-	struct nand_ecc_ctrl ecc;
1352
-	unsigned long buf_align;
1353
-	struct nand_controller dummy_controller;
1354
-
1355
-	uint8_t *bbt;
1356
-	struct nand_bbt_descr *bbt_td;
1357
-	struct nand_bbt_descr *bbt_md;
1358
-
1359
-	struct nand_bbt_descr *badblock_pattern;
1360
-
1361
-	void *priv;
1362
-
1363
-	struct {
1364
-		const struct nand_manufacturer *desc;
1365
-		void *priv;
1366
-	} manufacturer;
1062
+	int (*setup_interface)(struct nand_chip *chip, int chipnr,
1063
+			       const struct nand_interface_config *conf);
1367
1064
 };
1368
1065
 
1369
-static inline int nand_exec_op(struct nand_chip *chip,
1370
-			       const struct nand_operation *op)
1371
-{
1372
-	if (!chip->exec_op)
1373
-		return -ENOTSUPP;
1066
+/**
1067
+ * struct nand_controller - Structure used to describe a NAND controller
1068
+ *
1069
+ * @lock:		lock used to serialize accesses to the NAND controller
1070
+ * @ops:		NAND controller operations.
1071
+ */
1072
+struct nand_controller {
1073
+	struct mutex lock;
1074
+	const struct nand_controller_ops *ops;
1075
+};
1374
1076
 
1375
-	return chip->exec_op(chip, op, false);
1077
+static inline void nand_controller_init(struct nand_controller *nfc)
1078
+{
1079
+	mutex_init(&nfc->lock);
1376
1080
 }
1377
1081
 
1378
-extern const struct mtd_ooblayout_ops nand_ooblayout_sp_ops;
1379
-extern const struct mtd_ooblayout_ops nand_ooblayout_lp_ops;
1082
+/**
1083
+ * struct nand_legacy - NAND chip legacy fields/hooks
1084
+ * @IO_ADDR_R: address to read the 8 I/O lines of the flash device
1085
+ * @IO_ADDR_W: address to write the 8 I/O lines of the flash device
1086
+ * @select_chip: select/deselect a specific target/die
1087
+ * @read_byte: read one byte from the chip
1088
+ * @write_byte: write a single byte to the chip on the low 8 I/O lines
1089
+ * @write_buf: write data from the buffer to the chip
1090
+ * @read_buf: read data from the chip into the buffer
1091
+ * @cmd_ctrl: hardware specific function for controlling ALE/CLE/nCE. Also used
1092
+ *	      to write command and address
1093
+ * @cmdfunc: hardware specific function for writing commands to the chip.
1094
+ * @dev_ready: hardware specific function for accessing device ready/busy line.
1095
+ *	       If set to NULL no access to ready/busy is available and the
1096
+ *	       ready/busy information is read from the chip status register.
1097
+ * @waitfunc: hardware specific function for wait on ready.
1098
+ * @block_bad: check if a block is bad, using OOB markers
1099
+ * @block_markbad: mark a block bad
1100
+ * @set_features: set the NAND chip features
1101
+ * @get_features: get the NAND chip features
1102
+ * @chip_delay: chip dependent delay for transferring data from array to read
1103
+ *		regs (tR).
1104
+ * @dummy_controller: dummy controller implementation for drivers that can
1105
+ *		      only control a single chip
1106
+ *
1107
+ * If you look at this structure you're already wrong. These fields/hooks are
1108
+ * all deprecated.
1109
+ */
1110
+struct nand_legacy {
1111
+	void __iomem *IO_ADDR_R;
1112
+	void __iomem *IO_ADDR_W;
1113
+	void (*select_chip)(struct nand_chip *chip, int cs);
1114
+	u8 (*read_byte)(struct nand_chip *chip);
1115
+	void (*write_byte)(struct nand_chip *chip, u8 byte);
1116
+	void (*write_buf)(struct nand_chip *chip, const u8 *buf, int len);
1117
+	void (*read_buf)(struct nand_chip *chip, u8 *buf, int len);
1118
+	void (*cmd_ctrl)(struct nand_chip *chip, int dat, unsigned int ctrl);
1119
+	void (*cmdfunc)(struct nand_chip *chip, unsigned command, int column,
1120
+			int page_addr);
1121
+	int (*dev_ready)(struct nand_chip *chip);
1122
+	int (*waitfunc)(struct nand_chip *chip);
1123
+	int (*block_bad)(struct nand_chip *chip, loff_t ofs);
1124
+	int (*block_markbad)(struct nand_chip *chip, loff_t ofs);
1125
+	int (*set_features)(struct nand_chip *chip, int feature_addr,
1126
+			    u8 *subfeature_para);
1127
+	int (*get_features)(struct nand_chip *chip, int feature_addr,
1128
+			    u8 *subfeature_para);
1129
+	int chip_delay;
1130
+	struct nand_controller dummy_controller;
1131
+};
1380
1132
 
1381
-static inline void nand_set_flash_node(struct nand_chip *chip,
1382
-				       struct device_node *np)
1383
-{
1384
-	mtd_set_of_node(&chip->mtd, np);
1385
-}
1133
+/**
1134
+ * struct nand_chip_ops - NAND chip operations
1135
+ * @suspend: Suspend operation
1136
+ * @resume: Resume operation
1137
+ * @lock_area: Lock operation
1138
+ * @unlock_area: Unlock operation
1139
+ * @setup_read_retry: Set the read-retry mode (mostly needed for MLC NANDs)
1140
+ * @choose_interface_config: Choose the best interface configuration
1141
+ */
1142
+struct nand_chip_ops {
1143
+	int (*suspend)(struct nand_chip *chip);
1144
+	void (*resume)(struct nand_chip *chip);
1145
+	int (*lock_area)(struct nand_chip *chip, loff_t ofs, uint64_t len);
1146
+	int (*unlock_area)(struct nand_chip *chip, loff_t ofs, uint64_t len);
1147
+	int (*setup_read_retry)(struct nand_chip *chip, int retry_mode);
1148
+	int (*choose_interface_config)(struct nand_chip *chip,
1149
+				       struct nand_interface_config *iface);
1150
+};
1386
1151
 
1387
-static inline struct device_node *nand_get_flash_node(struct nand_chip *chip)
1388
-{
1389
-	return mtd_get_of_node(&chip->mtd);
1390
-}
1152
+/**
1153
+ * struct nand_manufacturer - NAND manufacturer structure
1154
+ * @desc: The manufacturer description
1155
+ * @priv: Private information for the manufacturer driver
1156
+ */
1157
+struct nand_manufacturer {
1158
+	const struct nand_manufacturer_desc *desc;
1159
+	void *priv;
1160
+};
1161
+
1162
+/**
1163
+ * struct nand_chip - NAND Private Flash Chip Data
1164
+ * @base: Inherit from the generic NAND device
1165
+ * @id: Holds NAND ID
1166
+ * @parameters: Holds generic parameters under an easily readable form
1167
+ * @manufacturer: Manufacturer information
1168
+ * @ops: NAND chip operations
1169
+ * @legacy: All legacy fields/hooks. If you develop a new driver, don't even try
1170
+ *          to use any of these fields/hooks, and if you're modifying an
1171
+ *          existing driver that is using those fields/hooks, you should
1172
+ *          consider reworking the driver and avoid using them.
1173
+ * @options: Various chip options. They can partly be set to inform nand_scan
1174
+ *           about special functionality. See the defines for further
1175
+ *           explanation.
1176
+ * @current_interface_config: The currently used NAND interface configuration
1177
+ * @best_interface_config: The best NAND interface configuration which fits both
1178
+ *                         the NAND chip and NAND controller constraints. If
1179
+ *                         unset, the default reset interface configuration must
1180
+ *                         be used.
1181
+ * @bbt_erase_shift: Number of address bits in a bbt entry
1182
+ * @bbt_options: Bad block table specific options. All options used here must
1183
+ *               come from bbm.h. By default, these options will be copied to
1184
+ *               the appropriate nand_bbt_descr's.
1185
+ * @badblockpos: Bad block marker position in the oob area
1186
+ * @badblockbits: Minimum number of set bits in a good block's bad block marker
1187
+ *                position; i.e., BBM = 11110111b is good when badblockbits = 7
1188
+ * @bbt_td: Bad block table descriptor for flash lookup
1189
+ * @bbt_md: Bad block table mirror descriptor
1190
+ * @badblock_pattern: Bad block scan pattern used for initial bad block scan
1191
+ * @bbt: Bad block table pointer
1192
+ * @page_shift: Number of address bits in a page (column address bits)
1193
+ * @phys_erase_shift: Number of address bits in a physical eraseblock
1194
+ * @chip_shift: Number of address bits in one chip
1195
+ * @pagemask: Page number mask = number of (pages / chip) - 1
1196
+ * @subpagesize: Holds the subpagesize
1197
+ * @data_buf: Buffer for data, size is (page size + oobsize)
1198
+ * @oob_poi: pointer on the OOB area covered by data_buf
1199
+ * @pagecache: Structure containing page cache related fields
1200
+ * @pagecache.bitflips: Number of bitflips of the cached page
1201
+ * @pagecache.page: Page number currently in the cache. -1 means no page is
1202
+ *                  currently cached
1203
+ * @buf_align: Minimum buffer alignment required by a platform
1204
+ * @lock: Lock protecting the suspended field. Also used to serialize accesses
1205
+ *        to the NAND device
1206
+ * @suspended: Set to 1 when the device is suspended, 0 when it's not
1207
+ * @resume_wq: wait queue to sleep if rawnand is in suspended state.
1208
+ * @cur_cs: Currently selected target. -1 means no target selected, otherwise we
1209
+ *          should always have cur_cs >= 0 && cur_cs < nanddev_ntargets().
1210
+ *          NAND Controller drivers should not modify this value, but they're
1211
+ *          allowed to read it.
1212
+ * @read_retries: The number of read retry modes supported
1213
+ * @controller: The hardware controller	structure which is shared among multiple
1214
+ *              independent devices
1215
+ * @ecc: The ECC controller structure
1216
+ * @priv: Chip private data
1217
+ */
1218
+struct nand_chip {
1219
+	struct nand_device base;
1220
+	struct nand_id id;
1221
+	struct nand_parameters parameters;
1222
+	struct nand_manufacturer manufacturer;
1223
+	struct nand_chip_ops ops;
1224
+	struct nand_legacy legacy;
1225
+	unsigned int options;
1226
+
1227
+	/* Data interface */
1228
+	const struct nand_interface_config *current_interface_config;
1229
+	struct nand_interface_config *best_interface_config;
1230
+
1231
+	/* Bad block information */
1232
+	unsigned int bbt_erase_shift;
1233
+	unsigned int bbt_options;
1234
+	unsigned int badblockpos;
1235
+	unsigned int badblockbits;
1236
+	struct nand_bbt_descr *bbt_td;
1237
+	struct nand_bbt_descr *bbt_md;
1238
+	struct nand_bbt_descr *badblock_pattern;
1239
+	u8 *bbt;
1240
+
1241
+	/* Device internal layout */
1242
+	unsigned int page_shift;
1243
+	unsigned int phys_erase_shift;
1244
+	unsigned int chip_shift;
1245
+	unsigned int pagemask;
1246
+	unsigned int subpagesize;
1247
+
1248
+	/* Buffers */
1249
+	u8 *data_buf;
1250
+	u8 *oob_poi;
1251
+	struct {
1252
+		unsigned int bitflips;
1253
+		int page;
1254
+	} pagecache;
1255
+	unsigned long buf_align;
1256
+
1257
+	/* Internals */
1258
+	struct mutex lock;
1259
+	unsigned int suspended : 1;
1260
+	wait_queue_head_t resume_wq;
1261
+	int cur_cs;
1262
+	int read_retries;
1263
+
1264
+	/* Externals */
1265
+	struct nand_controller *controller;
1266
+	struct nand_ecc_ctrl ecc;
1267
+	void *priv;
1268
+};
1391
1269
 
1392
1270
 static inline struct nand_chip *mtd_to_nand(struct mtd_info *mtd)
1393
1271
 {
1394
-	return container_of(mtd, struct nand_chip, mtd);
1272
+	return container_of(mtd, struct nand_chip, base.mtd);
1395
1273
 }
1396
1274
 
1397
1275
 static inline struct mtd_info *nand_to_mtd(struct nand_chip *chip)
1398
1276
 {
1399
-	return &chip->mtd;
1277
+	return &chip->base.mtd;
1400
1278
 }
1401
1279
 
1402
1280
 static inline void *nand_get_controller_data(struct nand_chip *chip)
..
..
@@ -1420,26 +1298,27 @@
1420
1298
 	return chip->manufacturer.priv;
1421
1299
 }
1422
1300
 
1423
-/*
1424
- * NAND Flash Manufacturer ID Codes
1425
- */
1426
-#define NAND_MFR_TOSHIBA	0x98
1427
-#define NAND_MFR_ESMT		0xc8
1428
-#define NAND_MFR_SAMSUNG	0xec
1429
-#define NAND_MFR_FUJITSU	0x04
1430
-#define NAND_MFR_NATIONAL	0x8f
1431
-#define NAND_MFR_RENESAS	0x07
1432
-#define NAND_MFR_STMICRO	0x20
1433
-#define NAND_MFR_HYNIX		0xad
1434
-#define NAND_MFR_MICRON		0x2c
1435
-#define NAND_MFR_AMD		0x01
1436
-#define NAND_MFR_MACRONIX	0xc2
1437
-#define NAND_MFR_EON		0x92
1438
-#define NAND_MFR_SANDISK	0x45
1439
-#define NAND_MFR_INTEL		0x89
1440
-#define NAND_MFR_ATO		0x9b
1441
-#define NAND_MFR_WINBOND	0xef
1301
+static inline void nand_set_flash_node(struct nand_chip *chip,
1302
+				       struct device_node *np)
1303
+{
1304
+	mtd_set_of_node(nand_to_mtd(chip), np);
1305
+}
1442
1306
 
1307
+static inline struct device_node *nand_get_flash_node(struct nand_chip *chip)
1308
+{
1309
+	return mtd_get_of_node(nand_to_mtd(chip));
1310
+}
1311
+
1312
+/**
1313
+ * nand_get_interface_config - Retrieve the current interface configuration
1314
+ *                             of a NAND chip
1315
+ * @chip: The NAND chip
1316
+ */
1317
+static inline const struct nand_interface_config *
1318
+nand_get_interface_config(struct nand_chip *chip)
1319
+{
1320
+	return chip->current_interface_config;
1321
+}
1443
1322
 
1444
1323
 /*
1445
1324
  * A helper for defining older NAND chips where the second ID byte fully
..
..
@@ -1473,10 +1352,10 @@
1473
1352
  * struct nand_flash_dev - NAND Flash Device ID Structure
1474
1353
  * @name: a human-readable name of the NAND chip
1475
1354
  * @dev_id: the device ID (the second byte of the full chip ID array)
1476
- * @mfr_id: manufecturer ID part of the full chip ID array (refers the same
1477
- *          memory address as @id[0])
1355
+ * @mfr_id: manufacturer ID part of the full chip ID array (refers the same
1356
+ *          memory address as ``id[0]``)
1478
1357
  * @dev_id: device ID part of the full chip ID array (refers the same memory
1479
- *          address as @id[1])
1358
+ *          address as ``id[1]``)
1480
1359
  * @id: full device ID array
1481
1360
  * @pagesize: size of the NAND page in bytes; if 0, then the real page size (as
1482
1361
  *            well as the eraseblock size) is determined from the extended NAND
..
..
@@ -1493,10 +1372,6 @@
1493
1372
  *               @ecc_step_ds in nand_chip{}, also from the datasheet.
1494
1373
  *               For example, the "4bit ECC for each 512Byte" can be set with
1495
1374
  *               NAND_ECC_INFO(4, 512).
1496
- * @onfi_timing_mode_default: the default ONFI timing mode entered after a NAND
1497
- *			      reset. Should be deduced from timings described
1498
- *			      in the datasheet.
1499
- *
1500
1375
  */
1501
1376
 struct nand_flash_dev {
1502
1377
 	char *name;
..
..
@@ -1517,117 +1392,9 @@
1517
1392
 		uint16_t strength_ds;
1518
1393
 		uint16_t step_ds;
1519
1394
 	} ecc;
1520
-	int onfi_timing_mode_default;
1521
1395
 };
1522
-
1523
-/**
1524
- * struct nand_manufacturer - NAND Flash Manufacturer structure
1525
- * @name:	Manufacturer name
1526
- * @id:		manufacturer ID code of device.
1527
- * @ops:	manufacturer operations
1528
-*/
1529
-struct nand_manufacturer {
1530
-	int id;
1531
-	char *name;
1532
-	const struct nand_manufacturer_ops *ops;
1533
-};
1534
-
1535
-const struct nand_manufacturer *nand_get_manufacturer(u8 id);
1536
-
1537
-static inline const char *
1538
-nand_manufacturer_name(const struct nand_manufacturer *manufacturer)
1539
-{
1540
-	return manufacturer ? manufacturer->name : "Unknown";
1541
-}
1542
-
1543
-extern struct nand_flash_dev nand_flash_ids[];
1544
-
1545
-extern const struct nand_manufacturer_ops toshiba_nand_manuf_ops;
1546
-extern const struct nand_manufacturer_ops samsung_nand_manuf_ops;
1547
-extern const struct nand_manufacturer_ops hynix_nand_manuf_ops;
1548
-extern const struct nand_manufacturer_ops micron_nand_manuf_ops;
1549
-extern const struct nand_manufacturer_ops amd_nand_manuf_ops;
1550
-extern const struct nand_manufacturer_ops macronix_nand_manuf_ops;
1551
1396
 
1552
1397
 int nand_create_bbt(struct nand_chip *chip);
1553
-int nand_markbad_bbt(struct mtd_info *mtd, loff_t offs);
1554
-int nand_isreserved_bbt(struct mtd_info *mtd, loff_t offs);
1555
-int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt);
1556
-int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
1557
-		    int allowbbt);
1558
-
1559
-/**
1560
- * struct platform_nand_chip - chip level device structure
1561
- * @nr_chips:		max. number of chips to scan for
1562
- * @chip_offset:	chip number offset
1563
- * @nr_partitions:	number of partitions pointed to by partitions (or zero)
1564
- * @partitions:		mtd partition list
1565
- * @chip_delay:		R/B delay value in us
1566
- * @options:		Option flags, e.g. 16bit buswidth
1567
- * @bbt_options:	BBT option flags, e.g. NAND_BBT_USE_FLASH
1568
- * @part_probe_types:	NULL-terminated array of probe types
1569
- */
1570
-struct platform_nand_chip {
1571
-	int nr_chips;
1572
-	int chip_offset;
1573
-	int nr_partitions;
1574
-	struct mtd_partition *partitions;
1575
-	int chip_delay;
1576
-	unsigned int options;
1577
-	unsigned int bbt_options;
1578
-	const char **part_probe_types;
1579
-};
1580
-
1581
-/* Keep gcc happy */
1582
-struct platform_device;
1583
-
1584
-/**
1585
- * struct platform_nand_ctrl - controller level device structure
1586
- * @probe:		platform specific function to probe/setup hardware
1587
- * @remove:		platform specific function to remove/teardown hardware
1588
- * @dev_ready:		platform specific function to read ready/busy pin
1589
- * @select_chip:	platform specific chip select function
1590
- * @cmd_ctrl:		platform specific function for controlling
1591
- *			ALE/CLE/nCE. Also used to write command and address
1592
- * @write_buf:		platform specific function for write buffer
1593
- * @read_buf:		platform specific function for read buffer
1594
- * @priv:		private data to transport driver specific settings
1595
- *
1596
- * All fields are optional and depend on the hardware driver requirements
1597
- */
1598
-struct platform_nand_ctrl {
1599
-	int (*probe)(struct platform_device *pdev);
1600
-	void (*remove)(struct platform_device *pdev);
1601
-	int (*dev_ready)(struct mtd_info *mtd);
1602
-	void (*select_chip)(struct mtd_info *mtd, int chip);
1603
-	void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
1604
-	void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
1605
-	void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
1606
-	void *priv;
1607
-};
1608
-
1609
-/**
1610
- * struct platform_nand_data - container structure for platform-specific data
1611
- * @chip:		chip level chip structure
1612
- * @ctrl:		controller level device structure
1613
- */
1614
-struct platform_nand_data {
1615
-	struct platform_nand_chip chip;
1616
-	struct platform_nand_ctrl ctrl;
1617
-};
1618
-
1619
-/* return the supported asynchronous timing mode. */
1620
-static inline int onfi_get_async_timing_mode(struct nand_chip *chip)
1621
-{
1622
-	if (!chip->parameters.onfi)
1623
-		return ONFI_TIMING_MODE_UNKNOWN;
1624
-
1625
-	return chip->parameters.onfi->async_timing_mode;
1626
-}
1627
-
1628
-int onfi_fill_data_interface(struct nand_chip *chip,
1629
-			     enum nand_data_interface_type type,
1630
-			     int timing_mode);
1631
1398
 
1632
1399
 /*
1633
1400
  * Check if it is a SLC nand.
..
..
@@ -1636,9 +1403,9 @@
1636
1403
  */
1637
1404
 static inline bool nand_is_slc(struct nand_chip *chip)
1638
1405
 {
1639
-	WARN(chip->bits_per_cell == 0,
1406
+	WARN(nanddev_bits_per_cell(&chip->base) == 0,
1640
1407
 	     "chip->bits_per_cell is used uninitialized\n");
1641
-	return chip->bits_per_cell == 1;
1408
+	return nanddev_bits_per_cell(&chip->base) == 1;
1642
1409
 }
1643
1410
 
1644
1411
 /**
..
..
@@ -1659,9 +1426,6 @@
1659
1426
 	return 0;
1660
1427
 }
1661
1428
 
1662
-/* get timing characteristics from ONFI timing mode. */
1663
-const struct nand_sdr_timings *onfi_async_timing_mode_to_sdr_timings(int mode);
1664
-
1665
1429
 int nand_check_erased_ecc_chunk(void *data, int datalen,
1666
1430
 				void *ecc, int ecclen,
1667
1431
 				void *extraoob, int extraooblen,
..
..
@@ -1671,37 +1435,26 @@
1671
1435
 			 const struct nand_ecc_caps *caps, int oobavail);
1672
1436
 
1673
1437
 /* Default write_oob implementation */
1674
-int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip, int page);
1675
-
1676
-/* Default write_oob syndrome implementation */
1677
-int nand_write_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1678
-			    int page);
1438
+int nand_write_oob_std(struct nand_chip *chip, int page);
1679
1439
 
1680
1440
 /* Default read_oob implementation */
1681
-int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip, int page);
1441
+int nand_read_oob_std(struct nand_chip *chip, int page);
1682
1442
 
1683
-/* Default read_oob syndrome implementation */
1684
-int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1685
-			   int page);
1686
-
1687
-/* Wrapper to use in order for controllers/vendors to GET/SET FEATURES */
1688
-int nand_get_features(struct nand_chip *chip, int addr, u8 *subfeature_param);
1689
-int nand_set_features(struct nand_chip *chip, int addr, u8 *subfeature_param);
1690
1443
 /* Stub used by drivers that do not support GET/SET FEATURES operations */
1691
-int nand_get_set_features_notsupp(struct mtd_info *mtd, struct nand_chip *chip,
1692
-				  int addr, u8 *subfeature_param);
1444
+int nand_get_set_features_notsupp(struct nand_chip *chip, int addr,
1445
+				  u8 *subfeature_param);
1693
1446
 
1694
-/* Default read_page_raw implementation */
1695
-int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1696
-		       uint8_t *buf, int oob_required, int page);
1697
-int nand_read_page_raw_notsupp(struct mtd_info *mtd, struct nand_chip *chip,
1698
-			       u8 *buf, int oob_required, int page);
1447
+/* read_page_raw implementations */
1448
+int nand_read_page_raw(struct nand_chip *chip, uint8_t *buf, int oob_required,
1449
+		       int page);
1450
+int nand_monolithic_read_page_raw(struct nand_chip *chip, uint8_t *buf,
1451
+				  int oob_required, int page);
1699
1452
 
1700
-/* Default write_page_raw implementation */
1701
-int nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1702
-			const uint8_t *buf, int oob_required, int page);
1703
-int nand_write_page_raw_notsupp(struct mtd_info *mtd, struct nand_chip *chip,
1704
-				const u8 *buf, int oob_required, int page);
1453
+/* write_page_raw implementations */
1454
+int nand_write_page_raw(struct nand_chip *chip, const uint8_t *buf,
1455
+			int oob_required, int page);
1456
+int nand_monolithic_write_page_raw(struct nand_chip *chip, const uint8_t *buf,
1457
+				   int oob_required, int page);
1705
1458
 
1706
1459
 /* Reset and initialize a NAND device */
1707
1460
 int nand_reset(struct nand_chip *chip, int chipnr);
..
..
@@ -1711,7 +1464,6 @@
1711
1464
 int nand_readid_op(struct nand_chip *chip, u8 addr, void *buf,
1712
1465
 		   unsigned int len);
1713
1466
 int nand_status_op(struct nand_chip *chip, u8 *status);
1714
-int nand_exit_status_op(struct nand_chip *chip);
1715
1467
 int nand_erase_op(struct nand_chip *chip, unsigned int eraseblock);
1716
1468
 int nand_read_page_op(struct nand_chip *chip, unsigned int page,
1717
1469
 		      unsigned int offset_in_page, void *buf, unsigned int len);
..
..
@@ -1731,25 +1483,64 @@
1731
1483
 				unsigned int offset_in_page, const void *buf,
1732
1484
 				unsigned int len, bool force_8bit);
1733
1485
 int nand_read_data_op(struct nand_chip *chip, void *buf, unsigned int len,
1734
-		      bool force_8bit);
1486
+		      bool force_8bit, bool check_only);
1735
1487
 int nand_write_data_op(struct nand_chip *chip, const void *buf,
1736
1488
 		       unsigned int len, bool force_8bit);
1489
+
1490
+/* Scan and identify a NAND device */
1491
+int nand_scan_with_ids(struct nand_chip *chip, unsigned int max_chips,
1492
+		       struct nand_flash_dev *ids);
1493
+
1494
+static inline int nand_scan(struct nand_chip *chip, unsigned int max_chips)
1495
+{
1496
+	return nand_scan_with_ids(chip, max_chips, NULL);
1497
+}
1498
+
1499
+/* Internal helper for board drivers which need to override command function */
1500
+void nand_wait_ready(struct nand_chip *chip);
1737
1501
 
1738
1502
 /*
1739
1503
  * Free resources held by the NAND device, must be called on error after a
1740
1504
  * sucessful nand_scan().
1741
1505
  */
1742
1506
 void nand_cleanup(struct nand_chip *chip);
1743
-/* Unregister the MTD device and calls nand_cleanup() */
1744
-void nand_release(struct nand_chip *chip);
1745
-
1746
-/* Default extended ID decoding function */
1747
-void nand_decode_ext_id(struct nand_chip *chip);
1748
1507
 
1749
1508
 /*
1750
1509
  * External helper for controller drivers that have to implement the WAITRDY
1751
1510
  * instruction and have no physical pin to check it.
1752
1511
  */
1753
1512
 int nand_soft_waitrdy(struct nand_chip *chip, unsigned long timeout_ms);
1513
+struct gpio_desc;
1514
+int nand_gpio_waitrdy(struct nand_chip *chip, struct gpio_desc *gpiod,
1515
+		      unsigned long timeout_ms);
1516
+
1517
+/* Select/deselect a NAND target. */
1518
+void nand_select_target(struct nand_chip *chip, unsigned int cs);
1519
+void nand_deselect_target(struct nand_chip *chip);
1520
+
1521
+/* Bitops */
1522
+void nand_extract_bits(u8 *dst, unsigned int dst_off, const u8 *src,
1523
+		       unsigned int src_off, unsigned int nbits);
1524
+
1525
+/**
1526
+ * nand_get_data_buf() - Get the internal page buffer
1527
+ * @chip: NAND chip object
1528
+ *
1529
+ * Returns the pre-allocated page buffer after invalidating the cache. This
1530
+ * function should be used by drivers that do not want to allocate their own
1531
+ * bounce buffer and still need such a buffer for specific operations (most
1532
+ * commonly when reading OOB data only).
1533
+ *
1534
+ * Be careful to never call this function in the write/write_oob path, because
1535
+ * the core may have placed the data to be written out in this buffer.
1536
+ *
1537
+ * Return: pointer to the page cache buffer
1538
+ */
1539
+static inline void *nand_get_data_buf(struct nand_chip *chip)
1540
+{
1541
+	chip->pagecache.page = -1;
1542
+
1543
+	return chip->data_buf;
1544
+}
1754
1545
 
1755
1546
 #endif /* __LINUX_MTD_RAWNAND_H */